The figure "A20 Pro will be 18% faster than A19 Pro" has been circulating online. But reading the Weibo post from Fixed Focus Digital (定焦数码) dated August 15, 2026—the source of this figure—neither A20 Pro nor A19 Pro is mentioned. The post only states that, regarding TSMC's first GAA (Gate-All-Around) process, "feedback from the supply chain" indicates roughly an 18% performance improvement and roughly a 30% reduction in power consumption.
Apple has not officially announced the A20 Pro or the iPhone 18 Pro. Neither the manufacturing process to be adopted nor the figures of 18% and 30% have been made public. Therefore, what needs to be verified here is not a performance prediction for the next-generation iPhone. Rather, it is how the figures from a supply chain post that reveals no source overlap with TSMC's publicly disclosed N2-generation metrics, and where the meaning diverges.
The Origin of the "18% Faster" Claim Names No A20 Pro
The Fixed Focus Digital post was published at 18:29 China time on August 15. Tagged with a hashtag suggesting "Apple secures priority adoption rights for TSMC's 2nm mass production," it touches on the GAA process that TSMC is adopting for the first time. The body of the post lists three points as feedback from the supply chain: approximately 18% performance improvement, approximately 30% reduction in power consumption, and a significant increase in Apple's procurement costs.
However, the post specifies neither the generation being compared against nor the measurement conditions. There are no product names like A20 Pro or A19 Pro, nor process names like N2 or N2P. In addition to the type of benchmark, it's unclear whether the comparison was made under equal power or equal speed conditions. It's also unknown whether the 18% performance figure and the 30% power figure hold simultaneously, or whether they refer to separate conditions.
This omission is not trivial. If product names are filled in, hearsay about a process generation ends up looking like measured values comparing specific, unannounced chips against each other. What the original post actually supports is only that an estimate of 18%/30% was mentioned regarding TSMC's 2nm process in general.
The post also references an increase in Apple's procurement costs. However, no amount is given. Manufacturing costs accumulate separately across wafer prices, per-die costs for good dies, and packaging expenses. Memory costs and final device pricing are also separate line items, and this single sentence cannot be used to derive the magnitude of increase in chip unit price or iPhone pricing.
N2 at 15%/30%, N2P at 18%/36%
Compared against the official metrics TSMC has previously disclosed, the 18%/30% figures in the original post do not form a single set of official numbers. According to TSMC's 2023 Tech Symposium materials, N2 targeted up to 15% faster speed at the same power versus N3E, or up to 30% power reduction at the same speed. These two figures are not a combination obtained simultaneously under the same conditions.
| Process | Compared Against | Performance | Power Consumption | Density | Conditions/Notes |
|---|---|---|---|---|---|
| N2 | N3E | Up to 15% faster at same power | Up to 30% reduction at same speed | Over 1.15x | TSMC's official 2023 target |
| N2P | N3E | 18% faster at same power | 36% reduction at same speed | Logic 1.2x, chip 1.15x | Uses the same design rules as N2 |
| Weibo post | Unknown | Approx. 18% improvement | Approx. 30% reduction | Not stated | Comparison target, conditions, and measuring party unknown |
On TSMC's current smartphone-oriented technology page, N2P is described as improving device performance by 5% relative to N2. However, this 5% figure is not accompanied by conditions such as fixed power. Looking at the comparison conditions against N3E on the HPC-oriented technology page, it shows 18% faster at the same power, or 36% power reduction at the same speed. The 18% figure overlaps with the original post, but the 30% figure does not match—these two improvement rates are under separate conditions.
An increase in density also does not directly translate to higher clock speeds. If more circuitry can be placed in the same area, designers may choose to add more compute units, or allocate the space to cache and additional features. There is also the option of shrinking the die to increase the number of chips obtained per wafer. Since the original post contains no information about density or die area, it's impossible to back-calculate the origin of the 18% figure from circuit scale.
Mass production timing also doesn't confirm which process will be adopted. According to TSMC's 2025 annual report, N2 is set to enter mass production with good yields in Q4 2025, with a rapid ramp-up expected in 2026. Meanwhile, N2P's mass production is scheduled for the second half of 2026. Both timings make it easy to associate them with next-generation products, but TSMC has not disclosed customer names.
In other words, the 18%/30% figures don't perfectly match either N2's 15%/30% or N2P's 18%/36%. N2P's mass production is scheduled for the second half of 2026, and TSMC expects N2P adoption to become the mainstream choice within the 2nm generation. Even so, the company has not explicitly named Apple or the A20 Pro as an adopting customer or product, and the mere proximity of the numbers cannot be used to conclude N2P adoption.
Process Headroom and Real-World Device Performance Are Different Things
GAA is the nanosheet-type transistor structure that TSMC's N2 adopts for the first time. Process performance/power metrics indicate how much headroom exists in transistors and circuit design under standard conditions. They are not results measured on a completed SoC with CPU, GPU, memory, and clock speed all fixed. They also don't account for the device's power budget, cooling method, or software.
This is also why TSMC's N2 materials separate "same power" from "same speed." Designers can direct headroom toward higher performance, or run the same performance at lower power. How the finished product allocates this trade-off between performance and power depends on the chip's configuration and the device design.
The current A19 Pro serves as a useful reference point for considering this distinction. Apple describes the A19 Pro as featuring a 6-core CPU, a 6-core GPU with Neural Accelerators, and a 16-core Neural Engine, claiming up to 40% higher sustained performance compared to the previous generation when combined with Apple's vapor chamber. This 40% figure is not the chip's standalone peak speed, but a comparison of sustained performance including cooling in the iPhone 17 Pro and 17 Pro Max.
Even if a future Apple SoC uses a 2nm-class process, there's no guarantee that a process-level 18% improvement would manifest identically across CPU and GPU. Nor can it be uniformly applied to sustained performance during AI processing or gaming. Similarly, a 30% reduction in power consumption does not mean a 30% increase in battery life, a 30% reduction in heat generation, or a 30% drop in the device's overall power consumption.
Before Price, Three Axes of Measurement
If Apple announces its next-generation Pro chip, the first things to examine should be performance figures broken down separately for CPU, GPU, and Neural Engine. Without knowing which block received the boost, the single phrase "performance improvement" cannot tell us how the change plays out across different use cases. A single one-off peak performance benchmark remains just one piece of material here as well.
Second, sustained performance is needed. As the A19 Pro's official description shows, under prolonged load, heat dissipation through the vapor chamber and chassis matters in addition to the chip itself. Without separately checking short-term maximum clock speed versus performance after sustained gaming or video processing, it's impossible to see how much of the process's headroom translates into real-world usable speed.
Third is the device's overall power and battery conditions. If screen brightness or network conditions differ between comparisons, the SoC's power efficiency alone cannot be isolated. Processing content and battery capacity also need to be matched. TSMC's figures are process metrics under fixed design conditions, and do not directly indicate iPhone usage time.
The same applies to procurement costs. The original post merely stated the direction of increase, without revealing which cost category or at what point in time the figure applies. The 18% figure can only be properly evaluated once peak performance, sustained performance, and device power can be compared under the same conditions.