DEEPX, the South Korean AI semiconductor company, has taped out its second-generation edge AI chip, the DX-M2, EE Times reported on November 9, 2026. Tape-out refers to the stage at which a chip design is complete and handed off to manufacturing. In Japan, reservations for evaluation samples have already opened, but this does not guarantee a formal order or delivery. DEEPX projects that combining the chip with PIM (Processing-in-Memory) technology, which handles part of the computation on the memory side, could raise AI generation speed by up to 6.7x. However, this figure is a simulation result that comes with higher power consumption, not performance confirmed on real hardware. Going forward, what matters is the configuration of the samples that are actually supplied, and how much performance the chip can deliver within the limited power budgets of edge devices.
Evaluation sample reservations open in Japan, delivery not yet confirmed
In Japan, reservations for the first engineering samples of the DX-M2 have already been announced. According to an announcement from Koshidatech, which handles domestic sales, the reservation process was announced on October 2, 2026, and samples are scheduled to be provided in the first half of 2027. However, a reservation is not a formal order or a guarantee of delivery, and because the DX-M2 itself is still in development, the sales price, final specifications, and specific supply timing have not been fixed. Nor does the reservation process guarantee that samples with a PIM-compatible configuration will be offered in Japan. For now, it is best understood as the start of a process aimed at companies that want to evaluate the product.
Later, EE Times' report of November 9 revealed that the DX-M2 tape-out is complete and that DEEPX is aiming to provide samples in March 2027 and begin mass production in the fall of that year. The "first half of 2027" announced for Japan and the "March 2027" reported by EE Times differ in scope and specificity, but they do not contradict each other. Both, however, are current plans and do not indicate firm sample delivery or mass-production dates.
PIM technology projected to raise AI generation speed 6.7x, with power consumption up 2.7x
The DX-M2 is a chip for edge AI, which runs AI on the device itself, such as robots and drones, rather than relying on the cloud. For such devices, what matters is not only a model's computational performance but also how efficiently the necessary data can be processed on limited power. In large language model (LLM) inference in particular, transferring model weights and other data from memory to the compute chip can limit both performance and power consumption. To address this issue, DEEPX is considering a configuration that pairs the chip with Samsung's LPDDR5x-PIM.
PIM is a technology that handles part of the computation traditionally performed on the processor side within the memory itself. By reducing the need to repeatedly transfer data from memory to the compute chip, it aims to improve processing efficiency. In DEEPX's concept, the matrix-vector multiplication (GEMV) used in AI inference is executed on the memory side. In LLM token generation, which requires repeatedly reading model weights, this could reduce the data-transfer burden.
According to EE Times, DEEPX projects from a simulation using Llama 3.1 8B that the configuration combined with LPDDR5x-PIM would generate at 6.7 times the speed of the DX-M2 alone. Here, generation speed refers to the number of tokens the AI can generate per second. Under these conditions, however, total system power consumption also rises 2.7x. The company says that even when compared at the same power budget, it expects a performance improvement of about 2x, but this too is a projection based on simulation.
Importantly, the 6.7x figure does not mean a performance gain achievable at the same power consumption. EE Times' report does not provide the absolute power consumption or measured token-generation speeds used in the comparison. The PIM compiler is also at a prototype stage, and a module for validating performance in a real hardware environment is said to be in preparation. Having PIM-capable memory samples available is a separate step from supplying systems that combine them with a finished DX-M2, so whether the projected figures can be reproduced on real hardware must await future verification.
The DX-M2 series comes in three configurations, and "5W" covers different scopes
DEEPX's official product page lists specifications for the DX-M2 as well as the "DX-M2M" and "DX-M2M Pro," which incorporate memory internally. All are products under development, and DX-M2M and DX-M2M Pro are provisional names. The models differ in memory capacity, bandwidth, and power configuration, and the power figures in particular require care. The 5W shown for the standard DX-M2 is for the SoC alone, whereas the 5W for the DX-M2M includes both the SoC and DRAM. Even though both say 5W, the scope of components differs, so power efficiency cannot be compared simply.
The main nominal specifications listed under "Chip Line-up" on the official page are as follows. All are at the development stage and may change.
| Product | Memory configuration / max capacity | Channels / max bandwidth | Power consumption and scope | Expected form factor |
|---|---|---|---|---|
| DX-M2 | External LPDDR5X, up to 96GB (24GB×4) | 8 channels, 153.6GB/s | 5W (SoC only) | M.2 / PCIe |
| DX-M2M (provisional) | Internal memory, up to 24GB | 4 channels, 76.8GB/s | 5W (SoC 3W + DRAM 2W) | M.2 |
| DX-M2M Pro (provisional) | Internal memory, up to 48GB | 8 channels, 153.6GB/s | 8.5W (SoC 4.5W + DRAM 4W) | M.2 |
The DX-M2 uses external LPDDR5X memory, with a capacity of up to 96GB and 153.6GB/s of bandwidth. The DX-M2M, by contrast, integrates up to 24GB of memory internally and puts the combined SoC and DRAM power consumption at 5W. The higher-end DX-M2M Pro offers up to 48GB of memory and 153.6GB/s of bandwidth, with combined SoC and DRAM power consumption rising to 8.5W. Consequently, multiplying the DX-M2's 5W by the 2.7x power factor for PIM use does not yield total system power consumption. The DX-M2's nominal figure excludes the power of external DRAM, so its measurement scope differs from the total power compared in the simulation.
In addition, the DX-M2M series, which incorporates memory internally, and PIM, which performs computation within memory, are different technologies. Integrating memory is a feature of layout and connection configuration and does not in itself imply PIM computation. The product specifications published so far show each model's memory configuration and nominal power consumption, and do not guarantee the generation speed or total power consumption when PIM is used.
What real hardware must show: generation speed and total system power
In its announcement for Japan, Koshidatech introduced a concept in which the DX-M2 supports AI models of up to roughly 100 billion parameters. This figure, however, assumes a model structure called MoE (Mixture of Experts). MoE uses only some of several specialized networks depending on the input, which keeps the number of parameters actually used in inference lower than the model's total. The explanation that it supports up to 100 billion parameters therefore does not mean all parameters can be computed every time. Nor can this supported scale be directly tied to the 6.7x PIM performance gain projected using an 8B model.
Edge AI has the advantage of processing AI on the device, which reduces latency from communicating with the cloud and lessens the need to send data externally. Koshidatech also expects deployment in such uses, but whether the chip can actually be adopted depends on the scale and accuracy of the models used, power consumption, heat, memory configuration, and other factors. In devices such as robots and drones in particular, the power and cooling available for AI inference are limited, so overall system efficiency matters as much as compute performance.
When evaluation samples become available, the first thing to confirm is whether they are the standard DX-M2, a memory-integrated type, or a PIM-compatible configuration. Generation speed and power consumption should then be measured with the same AI model, quantization conditions, input and output token counts, and concurrency. Quantization is a technique that lowers the numerical precision of a model's weights and computations to reduce required memory and computation, and inference performance varies with those conditions. Power consumption must be compared over a common scope that includes DRAM, not for the SoC alone.
At present, no independent real-hardware benchmarks of a DX-M2 combined with PIM, nor specific supply terms for the Japanese market, have been confirmed. Tape-out is an important milestone toward productization, but it does not mean the performance needed for mass production or commercial use has been demonstrated. Going forward, whether the projected generation speed can be reproduced on real hardware and fit within the power and thermal design constraints of the whole device will be a key factor in deciding whether to adopt the DX-M2 in actual edge AI products.