For edge AI devices that recognize images near cameras and sensors, the time from power-on to the first recognition result matters. Automotive surround-monitoring systems and industrial robots need to detect obstacles quickly, yet battery capacity and heat dissipation limits also require them to keep standby power low. Conventional systems, however, often combine DRAM, which loses its data when power is cut, with SSDs or flash memory, which retain data but are slow to read. That combination forces large amounts of data to be transferred at startup.
A research team led by Professor Tetsuo Endoh of the Center for Innovative Integrated Electronic Systems (CIES) at Tohoku University, together with Aisin Corporation, has developed an AI SoC built on a 16nm FinFET process that integrates 32MB of the non-volatile memory STT-MRAM. STT-MRAM stores data using the magnetization state of a magnetic material and retains its contents when power is off. The team stored the AI model's weight data and the boot data for a compact Linux in the on-chip MRAM, and adopted a Near-Memory Computing (NMC) approach that reads them without going through external DRAM or an SSD. As a result, the time from power-on to OS kernel startup fell to 65.7 ms, which the team confirmed is about 39 times faster than a conventional configuration.
However, the 65.7 ms figure is the time taken for the OS kernel to boot, not the time to complete object detection. The time from power-on to the first object detection result was 124.2 ms, which is also about 1/25 of the conventional configuration. In addition, these performance figures come from experiments running the lightweight object detection model Tiny YOLOv3 on an evaluation board. They do not represent performance in a commercial automotive ECU or consumer device. To evaluate the result properly, it is necessary to understand the scope of the processing that was measured and the design measures used to fit the model into on-chip memory.
- Conventional (external SSD + DRAM)
- Developed SoC (embedded STT-MRAM)
データを表で見る
| Conventional (external SSD + DRAM) (ms) | Developed SoC (embedded STT-MRAM) (ms) | |
|---|---|---|
| OS kernel boot time | 2,535.3 | 65.7 |
| AI processing time | 594.6 | 58.5 |
| Total system processing time | 3,129.9 | 124.2 |
Near-memory computing reduces data transfers to external memory
Deep learning models must hold millions to tens of millions of parameters (weight data) to perform tasks such as image recognition. In conventional edge AI devices, these parameters are typically stored in external NAND flash or an SSD, loaded into DRAM at power-on, and then fed to the processor's compute units. This approach requires large amounts of data to be transferred before computation can begin, increasing startup time and power consumption.
This problem is also related to the "von Neumann bottleneck," which arises from the gap between a processor's compute performance and the speed at which memory can supply data. The wiring between a processor and external memory has parasitic capacitance, and power is consumed as data moves across it. Even if an AI accelerator's compute performance improves, overall system performance does not rise sufficiently unless reading and transferring weight data can keep up. At startup in particular, reading data from external storage and initializing DRAM are required, so the time until inference can begin tends to grow.
The newly developed SoC integrates 32MB of STT-MRAM on the same silicon die as the processor, reducing its dependence on external memory. The chip carries a dual-core Arm Cortex-A53 CPU, an Arm Mali-G31 GPU, a dedicated AI accelerator, and 32MB of embedded STT-MRAM, and is manufactured on a 16nm FinFET process. By storing not only the AI model's weight data but also the data needed to boot the OS in the MRAM, the design eliminates the step of loading data from an external SSD into DRAM.
The defining feature of this design is near-memory computing (NMC). Unlike In-Memory Computing, which performs computation directly within memory cells, NMC places memory close to the compute circuits to reduce the distance and energy needed for data transfer. In this SoC, integrating large-capacity MRAM on the same chip as the compute units reduces the latency and power consumption associated with communicating with external memory. A key advantage is that the wiring used to exchange data can be shorter than in configurations that use external memory.
The AI accelerator also adopts a "4×4 tile weight-sharing technique." This reuses the weight data used in convolution operations locally, reducing how often the same data must be read repeatedly from memory. By reusing weights over multiple clock cycles, the design cuts the number of accesses to on-chip memory, improving efficiency in both memory bandwidth and power consumption.
OS boot about 39x faster, AI inference energy of 50.7 mJ/frame
In evaluating these gains, it is important to distinguish between OS boot time, AI processing time, and total system time. The conventional baseline the team compared against transfers 12MB of weight data from an external SSD to DRAM, boots the OS, and then runs inference. The developed SoC, by contrast, reads boot data and weight data directly from the embedded MRAM. The published materials report the following results for each stage.
First, the time from power-on until the compact Linux kernel boots fell from 2,535.3 ms with the conventional approach to 65.7 ms, a speedup of about 38.6 times. Keeping boot data in non-volatile MRAM eliminated the processing involved in reading from external storage and loading it into DRAM, which accounts for much of the gain.
AI processing time dropped from 594.6 ms with the conventional approach to 58.5 ms with the developed system, a speedup of about 10.2 times. However, the conventional measurement includes the time to transfer weight data from the SSD to DRAM. The roughly 10.2x difference therefore cannot be interpreted as an improvement in the AI accelerator's compute performance alone. It is a system-level comparison that also reflects the effect of eliminating data transfers from external memory.
The combined time for OS boot and AI processing, from power-on to the first object detection result, fell from 3,129.9 ms to 124.2 ms. That is a speedup of about 25.2 times: processing that previously took about 3.13 seconds now completes in about 0.12 seconds. For applications such as automobiles and industrial equipment, where responsiveness immediately after startup matters, shortening this overall wait time is significant.
For energy consumption, the team reported 50.7 mJ/frame for object detection with Tiny YOLOv3. The researchers say this cuts energy consumption to about 1/50 of the conventional approach. However, the published materials do not give detailed specifications for the peripheral circuitry, power-supply efficiency, or the range of equipment included in the measurement for the conventional system used as the comparison. Nor do they show variation or confidence intervals across repeated measurements, so the roughly 50x reduction should be read as a measured result under these particular evaluation conditions.
| Metric | Conventional (baseline) | Developed system | Reported change | Conditions / notes |
|---|---|---|---|---|
| OS kernel boot time | 2,535.3 ms | 65.7 ms | About 38.6x faster | From power-on to compact Linux kernel boot |
| AI processing time | 594.6 ms | 58.5 ms | About 10.2x faster | Conventional figure includes transferring 12MB of weights from SSD to DRAM |
| Total system time | 3,129.9 ms | 124.2 ms | About 25.2x faster | From power-on to first object detection result |
| AI energy per frame | Detailed value not disclosed | 50.7 mJ/frame | Reduced to about 1/50 | System-level measurement; conventional measurement conditions not described |
| Weight data size | 17.7MB | 9.36MB | About 47% smaller | Weight sharing and bit-width optimization applied |
| Object detection accuracy (mAP) | 0.325 | 0.316 | Down 0.009 | Evaluation dataset details and error ranges not described |
These figures show that fast startup from embedded MRAM and reduced access to external memory contribute to the system-level improvement. At the same time, the comparison of boot and AI processing times includes the presence or absence of data transfers, and so does not indicate a difference in the raw performance of the compute units. Moreover, the 50.7 mJ/frame energy figure and the 124.2 ms from power-on to first detection are different metrics and do not necessarily cover the same measurement scope. Judging real-world power efficiency will require additional evaluation suited to the application, such as power draw during continuous inference and wake-up from standby.
Weight sharing and mixed-precision arithmetic fit the AI model into 32MB of MRAM
The embedded STT-MRAM in this SoC has a capacity of 32MB. Storing all the parameters of a typical deep learning model at full precision would be difficult within that limit, and the larger the model, the harder it becomes to keep everything in on-chip memory. The team was able to run object detection without external DRAM or an SSD not just because it integrated MRAM, but because it combined that with circuit design that reduces the model's weight data.
The accelerator uses an "8/16-bit hybrid multiplication architecture" that switches bit widths as needed instead of fixing arithmetic precision. Specifically, it can switch between 16×16-bit, 16×8-bit, and 8×8-bit multiplication, reducing data volume and computational load according to the precision each operation requires. It supports operations that need 16-bit precision while improving efficiency where lower bit widths suffice. Combined with weight sharing, this reduced the total amount of parameters stored in on-chip memory.
According to the published materials, the weight data for Tiny YOLOv3 was compressed from the original 17.7MB to 9.36MB. That is about 53% of the original size, a reduction of about 47%. Keeping the model small made it possible to fit both the OS boot data and the AI model's weight data in the 32MB of embedded MRAM. The system's ability to run without external memory rests on both the memory integration technology and a design that reduces the model's data volume.
Compressing a model, however, involves a trade-off with recognition accuracy. The mAP (mean Average Precision), which measures object detection accuracy, was 0.325 for the original model and 0.316 after compression, a drop of 0.009. Although the decline was relatively small in this evaluation, the published materials do not specify the evaluation dataset, image resolution, or variation in the measurements. It is therefore unknown whether similar accuracy can be maintained in real road environments, against complex backgrounds, or when objects overlap.
The Tiny YOLOv3 used in the demonstration is also a relatively lightweight object detection model. The same compression ratio and performance gains will not necessarily be obtained with larger image recognition models or neural networks with different computational structures. The result shows that a specific model can fit into 32MB of MRAM and run without external DRAM; it does not demonstrate that the approach applies to every edge AI model.
Hopes for automotive AI, but durability and manufacturability must be verified
The results will be presented at the IEEE Asian Solid-State Circuits Conference (A-SSCC) 2026, an international conference on integrated circuits, held in Hsinchu, Taiwan, from November 1 to 4, 2026. The work has been accepted as an oral presentation in the "Domain-Specific Accelerators" session on November 2 (Paper 1014). At this stage it is a technical demonstration of a prototype chip through a conference presentation, and detailed results have not yet been published in a peer-reviewed journal.
Caution is also needed about the "world's first" positioning claimed by the research institutions, since it depends on the scope of the technologies and circuit configurations being compared. Processors using embedded MRAM and technologies that place non-volatile memory near compute circuits are already being researched by semiconductor makers and research institutions in Japan and abroad. To judge the novelty of this work, the conditions need to be considered separately: the 32MB embedded capacity, the 16nm FinFET process, the integration with an AI accelerator, and the demonstration of object detection without external memory.
The research involves Professor Endoh of Tohoku University's CIES and others, together with the major automotive supplier Aisin, and part of the work was supported by a commissioned project of the New Energy and Industrial Technology Development Organization (NEDO). Advanced driver-assistance systems (ADAS), automated parking systems, and industrial anomaly-detection cameras are conceivable applications where both fast startup and low power consumption are required. For devices that power on only when needed to run image recognition, in particular, shorter startup time could lead to power savings for the whole system. This announcement, however, does not indicate adoption in specific automotive products or mass-production plans.
Adopting it as an automotive semiconductor would require more than good results on a laboratory evaluation board. Automotive use demands stable operation across a wide temperature range, such as −40°C to 125°C depending on product requirements, as well as long-term data retention, write endurance, and operational reliability. STT-MRAM has the advantage of being non-volatile, but its data retention and write endurance are affected by temperature and usage conditions, so verification under realistic operating environments is essential. In addition, in a manufacturing process that embeds large-capacity STT-MRAM in a 16nm FinFET process, yield and cost will be important factors in any decision to mass-produce.
The significance of this result is that it shows an AI model and OS boot data can be held in the same chip's non-volatile memory, with object detection running without external DRAM or an SSD. It demonstrates the effectiveness of a design that improves the responsiveness and energy efficiency of edge AI by reducing startup data transfers and memory accesses, rather than just raising compute performance. For practical use, however, detailed measurement conditions need to be disclosed, and temperature and endurance testing for automotive environments, performance evaluation with other AI models, and manufacturing yield at volume production all need to be confirmed. If these challenges can be overcome, the technology could offer a new option for designing next-generation edge AI devices that need both fast startup and low power consumption.