The name "BFC," which appears to be attached to Intel's upcoming Nova Lake-S desktop CPUs with large caches, is drawing attention. A product list published by leaker LC Tech Leaks shows three models carrying the "BFC" suffix, along with the label "bLLC," which stands for a big last-level cache. However, neither the name nor the specifications have been officially announced by Intel, and the cache structure and whether any stacking technology is used remain unknown. The chips are expected to compete with AMD's Ryzen X3D series, but cache capacity alone does not determine real-world gaming performance. What matters is how quickly the CPU can fetch the data it needs, and how heat and power consumption are kept under control.
What Is "BFC" in Nova Lake-S? What the Leak Tells Us
On October 2, 2026 (Japan time), LC Tech Leaks posted on X a product list said to cover Intel's next-generation desktop CPU, Nova Lake-S.
The published image lists three products with "BFC" at the end of the model name, such as "4970K BFC." It also includes the label "bLLC," raising the possibility that BFC is a designation used to distinguish models with an enlarged cache.
However, the list does not state a specific cache capacity, nor does it explain what "BFC" stands for.
It is also unclear whether the BFC suffix will be used in the final product names. Various interpretations of the abbreviation are circulating, but at this point there is no basis for treating it as an official Intel technology name.
"bLLC," on the other hand, stands for "big Last Level Cache," meaning a large last-level cache.
The last-level cache is the lowest tier of the cache hierarchy, which the CPU checks before going out to main memory (DRAM) for data.
In typical desktop CPUs, the L3 cache fills this role, and increasing its capacity may reduce the number of accesses to main memory.
That said, increasing cache capacity and stacking separate semiconductor chips vertically are two different things.
Even if the goal is to boost gaming performance in the same way as AMD's 3D V-Cache, Intel will not necessarily adopt the same stacking approach.
Care is also needed when comparing cache capacities.
For example, Intel's official product information lists the Core Ultra 9 285K as having 36MB of Intel Smart Cache and 40MB of total L2 cache, in separate entries.
Even if a large cache figure is eventually announced for Nova Lake-S, its meaning will vary depending on whether it refers to the total L3 capacity, the amount of added cache, or a sum across multiple cache levels.
The leaked list alone does not allow us to judge that breakdown.
Does More Cache Mean Faster Games? Three Factors That Shape Performance
CPU cache affects gaming performance because of the waiting time involved in loading needed data.
When the CPU cannot find the data it needs in a cache, it must retrieve it from a lower-level cache or from main memory.
In particular, if the data is also absent from the last-level cache, DRAM access may be required, which can leave the CPU waiting for a long time.
Intel also explains in its memory access analysis documentation that last-level cache misses increase DRAM accesses, and that the resulting latency places a significant burden on performance.
A large cache can help in games because it may reduce these DRAM accesses.
For example, suppose data that a game references repeatedly doesn't fit in a conventional cache but does fit in an expanded one.
In that case, the CPU may need to go out to main memory less often, which could shorten processing wait times.
As a result, the calculations needed to render the next frame may finish sooner, which in some cases leads to higher frame rates.
However, doubling the cache capacity does not double gaming performance.
The actual effect depends on what data the game references and how often.
Also, even when the necessary data is in the cache, the read time is not zero.
Accessing the cache itself involves some latency, and when multiple CPU cores share the cache, contention for access may occur.
In other words, even if a larger cache reduces DRAM accesses, that alone cannot eliminate all waiting time.
When evaluating performance, it is necessary to distinguish at least the following three factors.
| Factor to evaluate | Main Intel VTune Profiler metric | What to check |
|---|---|---|
| Frequency of cache misses | LLC Miss Count | Whether the larger capacity reduced how often data isn't found in the last-level cache |
| Access latency to L3 cache | L3 Latency | Whether reading data takes a long time even when it is present in L3 |
| Stalls at L3 and contention between cores | L3 Bound | Whether access to L3 or contention with other cores is holding up processing |
These organize the performance analysis metrics Intel describes in its VTune Profiler documentation. They are not measured results from Nova Lake-S.
Note that L3 Latency is not the actual read time itself, but a metric showing the share of processing cycles involving L3 cache access under low load. L3 Bound also includes stalls from multiple causes, so that number alone cannot pinpoint contention between cores.
The available metrics also differ depending on the CPU design.
Seen this way, it is clear that comparing Intel and AMD CPUs with large caches cannot be done on simple capacity alone.
A larger cache may allow more data to be held close to the CPU. But which cores can use that data, and how quickly it can be retrieved, depends on the cache's connection structure and sharing scheme.
Even with the same cache capacity, gaming performance will differ if data placement and access paths differ.
Furthermore, even if the CPU side becomes faster, the frame-rate improvement may be small if the GPU's rendering capability is already maxed out.
For that reason, benchmarks under conditions where CPU differences show up readily and benchmarks at the resolutions and quality settings users actually play at can tell us different things.
To understand how useful a large cache really is, both kinds of testing are needed.
Why AMD Placed 3D V-Cache Beneath the CPU Cores
When considering Intel's large-cache plans, AMD's "3D V-Cache" is the natural point of comparison.
AMD's second-generation 3D V-Cache uses a structure that places the additional cache beneath the CPU cores.
According to AMD's technical explanation, the technology combines a CCD with up to eight Zen 5 CPU cores and a 64MB L3 cache die.
A CCD is a chiplet that groups CPU cores, and a die is a silicon chip on which semiconductor circuits are formed.
The CPU cores and the additional cache are connected through through-silicon vias (TSVs) and direct copper-to-copper bonding.
The key point of this structure is that the additional cache sits below the CPU cores.
According to AMD, this makes it easier to dissipate heat from the CPU cores to the cooler, improving cooling performance.
Increasing cache is a technique for keeping more data close to the CPU, but it also raises the question of where to place the CPU cores that generate the heat.
A structure that is easier to cool may also help in sustaining high clock speeds.
For that reason, even if Intel does not adopt stacking, one cannot simply conclude that it is "advantageous for cooling because it isn't stacked."
AMD itself has improved its thermal design by revisiting the positional relationship between the CPU cores and the cooler while keeping the stacked cache.
Actual cooling performance and sustained clock speeds are not determined solely by whether the cache is laid out flat or stacked.
As for how Intel's cache expansion may affect chip area, earlier leaks offer a reference.
Hardware leaker HXL, in a post on X dated February 11, 2026, reported that the standard version with eight P-cores and 16 E-cores would have a die area of just over 110mm², while the bLLC version would be just over 150mm².
However, these were unconfirmed reports at the time and do not represent the die area of the final product.
A difference in die area also does not settle how the cache is implemented.
If Intel adopts a method of adding cache on the same die as the CPU cores, a larger die area would be needed to hold the additional cache.
In general, the larger the die area, the fewer chips can be made from a silicon wafer of the same size, which can affect manufacturing cost.
On the other hand, a method that stacks a separate cache die involves the processes and costs of bonding the chips together.
Which approach is more advantageous on cost depends on the manufacturing process, yields and other factors. The leaked die-area figures alone therefore cannot predict Intel's product pricing or profit margins.
The competition over large caches is not simply a race to add more memory capacity; it is also a technology contest over achieving high processing performance and suitable operating temperatures while keeping manufacturing costs in check.
What Intel needs is not to build a cache with the same structure as AMD's.
What matters is balancing clock speeds, power consumption and manufacturing cost while reducing data access wait times.
What Will Be Needed to Judge Intel's Ryzen X3D Rival
When Intel eventually announces official specifications for BFC models, it will be worth watching not only the cache capacity but also how it is shared.
For example, even if a CPU's total cache is large, it does not necessarily mean all cores running a game can access the full capacity under the same conditions.
In a design that combines multiple compute tiles or chiplets, where data is stored and whether access to another tile is required will also matter.
For the specific cache-sharing scope and data transfer paths of Nova Lake-S, we will have to wait for official technical documentation from Intel.
When comparing gaming performance, attention should also go beyond average frame rates to the time taken to render each frame.
If a large cache reduces data-loading waits, the average frame rate may improve only slightly, yet the long stalls that occur in some frames could shrink, making gameplay smoother.
However, frame time is also influenced by GPU rendering load and game-engine processing.
Therefore, an improvement in frame time alone cannot be attributed entirely to the larger cache.
When comparing a standard model with a large-cache model, actual clock speeds and power consumption also need attention.
For example, even if the model with more cache is faster, if the clock speeds also differ, the performance gap cannot be credited entirely to cache capacity.
On the other hand, if the same performance can be achieved at lower power consumption, that would be a major advantage for users who value cooling performance and quiet operation.
Pricing, too, should be evaluated not just on the performance gap but also on benefits in power consumption and cooling.
The leaked "BFC" name suggests Intel may introduce special models equipped with large caches.
They are expected to compete with AMD's Ryzen X3D series, but for now their specific cache structure, performance and price remain unknown.
In the end, what matters is not how large the cache is, but how smoothly games actually run.
Once official specifications are released and comparisons of gaming performance, power consumption and price under identical conditions become possible, we will be able to see how competitive Intel's large-cache strategy is against AMD's 3D V-Cache.