Regarding "Razor Lake," reportedly Intel's next-next-generation client CPU, Commercial Times (工商時報) reported on August 20, 2026, citing supply chain sources, that it may adopt TSMC's N2X process. According to this view, Nova Lake would combine Intel 18A with TSMC N2P, while the following Razor Lake would additionally adopt N2X. However, Intel has not disclosed the product name, the process to be used, or the allocation across dies or SKUs. The report does not mention Intel's stated condition that this depends on "how 18A-P performs," and factors beyond yield and cost—including manufacturing capacity—could also affect the decision. How much weight is given to launch timing and the burden of design migration also remains unclear. Because the published figures for 18A-P and N2X use different measurement baselines, manufacturing allocation cannot be predicted from numbers alone.
The Scope of the Manufacturing Split Reported by Commercial Times
Commercial Times reported that Nova Lake would combine Intel 18A with TSMC N2P, and that Razor Lake might use N2X. The report does not specify what would be allocated to which process in Nova Lake, which die or SKU in Razor Lake would use N2X, or what proportion would be involved. Nor is this an official Intel announcement.
The outlet also presented an industry view suggesting that outsourcing part of the compute die could help adjust launch timing, performance, and manufacturing capacity while reducing dependence on a single process. This is not an explanation from Intel itself. It also remains unclear whether the "combination" mentioned in the report means the same compute die could be swapped between the two companies' manufacturing processes, or whether different dies would be built separately by SKU or by tile.
Intel's 2025 Form 10-K explains that many of its products use a disaggregated architecture that integrates multiple dies or tiles. While 18A and 18A-P are described as important processes across multiple future generations of client/server CPUs, the filing also states that for future products requiring performance beyond 18A-P, Intel intends to retain the option of using either its internal node or an external foundry. This general policy does not confirm which foundry Razor Lake will use, but it does provide context for why a product cannot be described using a single manufacturing node alone.
N2X Is a 2nm Derivative Aimed at Maximum Frequency
TSMC states that N2 entered mass production in 2025. N2P is a derivative that keeps the same design rules as N2 while improving performance by 5%. Compared to N3E, TSMC also states that N2P delivers 18% higher speed at the same power, 36% lower power at the same speed, 1.2x logic density, and 1.15x chip density.
N2X is a separate derivative that TSMC describes for high-performance computing applications. It combines two elements—ultra-high-performance standard cells and high-speed devices—each contributing 5%, for a combined 10% speed improvement. The high-speed devices are selectively inserted into critical paths to limit power overhead. What can be read from TSMC's public information is only that this is an option for extracting performance in designs that require maximum frequency; it does not indicate adoption in Razor Lake or any mass-production allocation.
Naming also requires caution here. The "N2P V2" designation mentioned later, which comes from a separate information stream, is not an official N2P or N2X classification found on TSMC's public pages. N2P and N2X cannot be treated as the same thing, nor can a post-correction name be treated as TSMC's official process designation.
18A-P's 9% and N2X's 10% Are Not Measured on the Same Scale
On June 16, 2026, Intel announced that 18A-P had entered risk production. Compared to 18A, it offers either 9% higher performance at the same power or 18% lower power at the same performance. Intel also states that thermal resistance improves by 20–40% and via resistance by 10–30%, while maintaining design rule compatibility with 18A.
18A-P is not a process being built from scratch without any mass-production track record. According to Intel's 2025 Form 10-K, the underlying 18A process entered mass production in the second half of 2025 and was used in the first Intel Core Ultra Series 3 products. 18A-P is a derivative that can inherit that design foundation. However, 18A's mass-production track record cannot be used to infer either 18A-P's adoption in Razor Lake or an equivalent yield.
Meanwhile, N2X's 10% figure represents the combined speed improvement TSMC attributes to N2X's two elements. 18A-P's 9% figure is performance at equal power relative to 18A as the baseline—neither the denominator nor the measurement conditions match N2X's 10%. Similarly, N2P's 18% and 36% figures are relative to N3E. Simply placing these numbers side by side cannot determine which is faster, which uses less power, or which is more advantageous as a product.
The means of extracting performance also differ. Intel describes 18A-P as combining transistor, interconnect, and design-manufacturing co-optimization, along with a "Power Boost" feature that uses low-resistance dual contacts to increase drive current and frequency. TSMC's N2X selectively inserts high-speed devices into necessary critical paths. Both are process-side design tools, not figures that guarantee the final CPU's clock speed or power consumption.
18A-P's design rule compatibility is also an internal matter within the Intel 18A family, intended to make design assets from 18A easier to reuse. It does not mean the same die could easily be ported to TSMC's N2 family. Cross-foundry interchangeability has not been disclosed, and the actual product performance, yield, and cost also remain unpublished.
Whether This Counts as Dual Sourcing Awaits Die- and SKU-Level Information
Intel's tile-based products leave room for assigning different manufacturing nodes to different tiles. That alone, however, does not mean Commercial Times' report can immediately be called confirmation of "dual sourcing." The implications for design, verification, and supply risk differ depending on whether the same compute die can be dual-sourced, whether different dies are allocated to different SKUs, or whether roles are divided by tile.
Using an external foundry also involves separate conditions such as supply capacity and pricing. In its Form 10-K, Intel discloses that it has no long-term contract with TSMC, and that failing to secure sufficient manufacturing capacity at favorable prices could pose a risk affecting product volume and cost. Even if outsourcing were to increase, it would not be a simple decision based on performance alone.
Intel's 18A-P is still at the risk production stage. TSMC's official explanation of N2X likewise only describes the technology's composition and performance targets, without revealing production plans for any specific customer. Determining the manufacturing split would require, in addition to each process's published performance figures, information on which die of which product will be made, when, and in what volume.
Two Separate N2X Rumors Exist, and One Was Corrected
Separately from Commercial Times' report, an N2X rumor about Razor Lake originating from Jaykihn had also circulated. Tom's Hardware, in an update at noon ET on August 18, 2026, recorded that this source had corrected the manufacturing process information from N2X to "N2P V2." This correction does not retract Commercial Times' report. The two pieces of information do not share the same basis, nor do they corroborate each other.
What remains is Commercial Times' report presenting the possibility of N2X adoption in Razor Lake. With no announcement from Intel at this time, what can be confirmed is only that 18A-P, an internal process improving on 18A, has entered risk production, and that TSMC describes N2X as an N2 derivative aimed at high performance. The real picture of Razor Lake can only be verified once Intel discloses the product name, launch timing, die configuration, and manufacturing allocation.