Jeff Dean, who has led AI development at Google, has outlined an idea for designing chips with far fewer people in far less time. According to a transcript of a conversation published by OpenXLA in September, if a system that automatically explores design candidates becomes fast enough, a project that now takes 150 people two years could in principle be done by 10 people in three months. This is not an achievement already in hand. It is an assumption about what could happen if design automation advances. Google already uses AI to improve chip layout and circuits, but extending those partial successes to an entire chip requires speeding up not only how fast candidates are generated, but also how fast their correctness can be confirmed.
What the "10 people, 3 months" idea involves
In the OpenXLA conversation, Dean discussed building specialized chips, tuned to particular computations, quickly enough to keep pace with changing uses. Narrowing a design to a specific workload makes it easier to gain efficiency, but the AI computations people want to run may change while the design is being carefully developed. By the time the chip is finished, the assumptions made at the start may be out of date.
The transcript describes a flow in which people write a specification into RTL, a separate team verifies that it is correct, and the circuit is then placed. RTL is a way of describing a design, specifying how data moves and is processed inside a circuit. The core of the idea is to make it possible to explore, using reinforcement learning or evolutionary methods, a process that currently involves repeated human conversion and checking.
For that to work, the process of evaluating candidates must also be fast. Dean also mentioned the execution speed of current EDA (electronic design automation) tools. The weight of evaluation time differs between using tools so that people narrow down candidates before examining them in detail, and using them so that machines try large numbers of candidates repeatedly.
The figure of 10 people and 3 months is an illustration of what could happen if these conditions are met. It is not a report of a completed design for a specific chip, nor a plan to cut a 150-person team down to 10.
How far has automation actually come?
AlphaChip, which Google DeepMind described in September 2024, handles floorplanning, which decides the placement of circuit blocks inside a chip. It places components one after another and learns using the quality of the finished layout as a reward. According to the company, it is pre-trained on earlier blocks and then applied to new ones, and has been used in designing TPUs.
Changing the placement alone changes how wires connect. Still, deciding placement is a different job from deciding what a chip should do and writing the circuit itself. Google's description of generating a layout in hours, compared with weeks or months of human work, also refers to the placement step. It does not mean that overall chip development has been cut to hours.
AlphaEvolve is an example that goes into circuit description. In its official explanation from May 2025, it rewrote an arithmetic circuit used for matrix multiplication in Verilog, a hardware description language, and proposed removing unnecessary bits. After the change, the circuit's function was verified as correct, and it was reportedly adopted in a TPU then under development. In an update in May 2026, Google said it had become a tool in continuous use when optimizing the design of a next-generation TPU.
Another technology bridging specification and circuit is Google's XLS. It is a high-level synthesis system that generates Verilog and other outputs from a high-level functional description, and it is not a product in which AI autonomously completes a chip. It helps run the same design as software and formally check whether function is preserved before and after conversion.
| Technology and reference date | What it automates | Output and how it is checked | Why it can't be read as overall development time |
|---|---|---|---|
| AlphaChip / Google DeepMind, September 2024 | Placement of circuit blocks | Learns from layout quality as a reward; described as used in TPU design | Not a demonstration that it replaces specification or overall functional design |
| AlphaEvolve / Google DeepMind, May 2025 | Improvement of arithmetic circuit descriptions | Verilog modifications verified for function before being adopted, as described | An improvement to part of a circuit, not the result of designing a whole chip from scratch |
| XLS / Google public README, checked September 22, 2026 | Conversion from high-level description to circuit | Generates circuit descriptions and helps confirm functional equivalence | An experimental project, not an officially supported Google product |
AlphaChip handles placement, AlphaEvolve improves circuit descriptions, and XLS converts high-level descriptions into circuits. Because they target different stages, they cannot be equated with shortening the design time of an entire chip.
The table classifies the target, output and verification method described in each linked official explanation and in the XLS README by stage; it is not a comparison of speed under identical conditions. The adoption of AlphaChip and AlphaEvolve is also Google's own account. Even so, it shows that automation has spread beyond placement to circuit modification and conversion from high-level descriptions.
Designing fast requires a way to check fast
AlphaEvolve's circuit modifications are not adopted just as generated. Google states explicitly that they must pass verification confirming that the function remains correct after modification. The role of proposing new candidates through exploration is separate from the role of deciding whether they can be adopted.
This distinction has practical implications for expanding design automation. Even if large numbers of candidates can be generated, if checking each one takes a long time, the number of candidates that can be tried is unlikely to grow. Conversely, running only simplified evaluations quickly does not guarantee that a candidate judged good by them will meet real requirements. Dean's idea of fast exploration is best read as a challenge of improving candidate generation and evaluation together.
The equivalence checking that XLS supports also has a defined scope. Confirming that a converted circuit has the same function as a reference description is a different task from judging whether the reference specification suits the processing the user needs. A circuit faithful to its specification is useless if the intended use was chosen wrongly. Nor does confirming functional match guarantee power consumption or post-manufacturing yield.
Shortening design also does not automatically shorten the time it takes a factory to make the chip. In a separate February 2025 Dwarkesh Podcast, Dean explained that manufacturing at leading-edge nodes takes three to five months. That was a remark from that time and not a guarantee of current manufacturing lead times, but it shows that design and manufacturing need to be considered separately. The assumption of "design in three months" cannot be swapped for a promise that mass-produced chips arrive in three months.
Beyond smaller teams: keeping up with changing uses
The value of speeding up specialized chip design cannot be measured only by reduced headcount. In light of the problem Dean raised, that the intended computation changes before a chip is finished, being able to update designs on a short cycle is itself valuable. It reduces the burden of predicting far ahead to decide functions, and lets designs be tailored to the processing needed at the time.
However, even if a small design team becomes viable, it would need evaluation compute and design tools behind it. From the headcount and timeline alone, it is not possible to calculate the reduction in overall development cost or the effect on employment in the semiconductor industry. Whether automation reduces human work or lets the same number of people try more designs will also depend on actual operation.
To judge practical viability, we need results showing for what scale of chip, what was automated from specification to verified design, and where people intervened. If it can further be confirmed that design-time evaluations match post-manufacturing behavior, the idea of producing specialized chips on a short cycle could become a concrete option for keeping pace with fast-changing AI workloads.