On October 8, 2026, GlobalFoundries (GF) announced a $2 billion agreement to manufacture silicon interposers in the United States for TSMC's advanced packaging technology, CoWoS. GF will handle production at its Malta, New York fab and plans to begin ramping up volume production in the first half of 2028. A silicon interposer is a key component that connects compute chips and memory at high density. Even if compute chips can be made at TSMC's Arizona fab, completing an AI chip also requires the components that connect chips and the assembly and testing steps. The agreement is a step toward linking those processes inside the US and building out a supply system for AI chips.
A $2 billion deal expands US supply of the parts that connect chips
Under the agreement, GF will manufacture silicon interposers for TSMC and expand production capacity at its Malta, New York fab. The initial term of the contract is five years, and the framework also allows capacity to be expanded in the future as demand grows.
In the semiconductor manufacturing process, GF's role is neither making the compute chips themselves nor assembling multiple chips into a single package. It is manufacturing the component that sits between those steps and connects the chips to each other.
Note that the $2 billion figure represents the scale of the manufacturing contract, not the capital investment in the Malta fab. The breakdown of payments and annual supply volumes have not been disclosed, so annual revenue or the scale of capacity expansion cannot be calculated from this figure. Nor is there any basis for interpreting the initial five-year term as running for five years from 2028, when volume production is slated to begin.
GF describes the plan as establishing the first US-based silicon interposer supply site that supports advanced packaging technology, including embedded deep trench capacitors (eDTC).
However, this "first in the US" positioning refers to the technology and use case GF is targeting here. It does not mean that no technology for connecting semiconductor chips has ever existed in the US.
Silicon interposers support data transfer and power stability
TSMC's CoWoS is an advanced packaging technology that combines compute chips with stacked high-bandwidth memory (HBM) chips and other components into a single package.
Within it, the silicon interposer connects chips to one another through fine wiring. Even if a compute chip is high-performance, it cannot realize its full capability unless it can receive the data it needs from memory at sufficient speed. For this reason, the wiring structure inside the package is also a key factor in AI chip performance.
Silicon interposers also help stabilize power delivery. TSMC's 2021 research overview on CoWoS-S describes the integration of multiple chips using through-silicon vias (TSVs) and high-density copper wiring. It also introduces technology that improves power stability through integrated capacitors.
In other words, a silicon interposer is involved not only in moving data quickly between compute chips and memory, but also in supplying the power that lets the chips operate stably.
However, CoWoS comes in several variants, and not all of them use the same interposer structure. TSMC's 2025 annual report describes the main variants as follows.
| Variant | Connecting component structure |
|---|---|
| CoWoS-S | Uses a silicon interposer with high-density wiring and embedded deep trench capacitors (eDTC) |
| CoWoS-R | Connects chips through an interposer using multiple redistribution layers (RDL) |
| CoWoS-L | Combines an RDL-based interposer with local silicon interconnects (LSI), eDTC, and other elements |
Source: TSMC 2025 Annual Report, description of 3DFabric on page 102. This compares the structures of each variant and does not indicate which variant the GF agreement covers.
These structural differences also matter when considering what effect the agreement will have.
GF's announcement does not specify which CoWoS variant the silicon interposers it will supply are for, nor does it name specific customer products. It is therefore not possible to conclude that the parts are dedicated to CoWoS-S, nor to assume that the same structure is used in CoWoS-L.
Increasing the supply capacity of silicon interposers is also a separate matter from increasing the capacity to assemble finished packages. Capacity expansion needs to be confirmed for each process.
How far will the US semiconductor supply chain come together by 2028?
Organizing the plans announced so far by manufacturing step, wafer production for compute chips is ahead in the US. Meanwhile, new capacity for manufacturing connecting components and for assembling and testing advanced packages is expected to come online in 2028.
On October 17, 2025, NVIDIA announced that production of Blackwell wafers at TSMC's Phoenix, Arizona fab had reached volume production.
Amkor Technology, which handles package assembly and testing, plans to begin production at the first phase of its new campus under construction in Peoria, Arizona in early 2028.
On June 16, 2026, TSMC and Amkor also announced a 10-year partnership agreement. It establishes a framework under which TSMC procures advanced packaging and testing services from Amkor.
| Manufacturing step | US site / company | Disclosed status or plan | Source |
|---|---|---|---|
| Compute chip wafer manufacturing | Phoenix, Arizona – TSMC | Blackwell wafers have reached volume production | NVIDIA, October 17, 2025 |
| Silicon interposer manufacturing | Malta, New York – GF | Volume production ramp-up scheduled to begin in the first half of 2028 | GF, October 8, 2026 |
| Package assembly and testing | Peoria, Arizona – Amkor | Phase 1 facility scheduled to begin production in early 2028. Procurement agreement with TSMC signed | Amkor, October 6, 2025, TSMC and Amkor, June 16, 2026 |
This table organizes information disclosed as of October 9, 2026, by manufacturing step, location, and operating status. Each company's results and plans do not necessarily target the same AI chip, and it has not been confirmed that the three sites can be used together to mass-produce a single product. The announcement also does not specify a concrete route for delivering components from GF to Amkor.
Still, it is clear that a system for manufacturing advanced semiconductors in the US is gradually taking shape. The GF agreement supports the procurement of connecting components, and the Amkor agreement supports the assembly and testing steps. Because each covers a different process, neither agreement alone can show how much finished-product supply capacity will increase.
TSMC has also indicated a policy of building its own advanced packaging facilities in the US. Its expanded US investment plan announced in March 2025 includes the construction of two advanced packaging facilities.
Amkor is also expanding its capital investment plans. In October 2025, it announced a plan to invest a total of $7 billion across two phases at its new Arizona campus, and on September 8, 2026, it formally announced the Phase 2 expansion, raising the total planned investment to about $12 billion. Construction of the Phase 2 facility is to begin at the end of 2027, with completion targeted by the end of 2029.
However, the dollar figures mean different things for TSMC's and Amkor's capital investment plans and for GF's $2 billion manufacturing contract. Simply adding them together would not yield a number that represents the CoWoS production capacity being built in the US.
GF, which abandoned 7nm development, will now support TSMC's advanced AI chips
The agreement is also interesting in light of the business strategy GF has pursued until now.
In August 2018, GF announced that it was indefinitely halting development of its 7nm FinFET technology. It shifted away from pursuing the leading edge of process miniaturization and decided to concentrate development resources on improving its 14/12nm processes and on technologies with strengths in specific applications, such as radio-frequency (RF) technology.
This was a strategic shift from competing at the cutting edge of miniaturization to building competitiveness around the functions and applications that customers need.
Now GF will supply advanced packaging components to TSMC, which manufactures cutting-edge compute chips.
Not every semiconductor maker needs to join the race for the most advanced miniaturization to capture demand for AI chips. TSMC has strengths in manufacturing compute chips, while GF supplies the components needed to combine those chips into a single package. It is a relationship in which companies with strengths in different technologies each play their own role.
In particular, for high-performance AI chips, efficiently connecting multiple compute chips and HBM has become important. Even if the compute chip itself is high-performance, it is difficult to increase finished-product volume production without securing enough of the components that connect them.
GF's role here is to make it possible to source these key components within the US. It can be seen as a move that lets GF join the advanced AI chip supply chain by leveraging its own manufacturing technology, rather than re-entering the development of advanced logic such as 7nm.
On the other hand, increasing manufacturing sites in the US is not the same as increasing the options for packaging technology.
The agreement establishes a new supply site in the US to support TSMC's CoWoS; it does not enable a shift to a different packaging method. It can be expected to help diversify component sourcing geographically, but it does not eliminate dependence on a particular technology.
Whether the $2 billion deal pays off depends on volume production after 2028
The first half of 2028, GF's planned timing, is a target for starting the ramp-up to volume production. It is not a commitment to the point at which a sufficient quantity of good units can be shipped reliably.
The timing is also close to early 2028, when Amkor aims to begin production at its Phase 1 facility, but there is no guarantee that each company's facilities will run at the same time and be usable for volume production of the same customer product.
To gauge future progress, it will first be important to see which CoWoS variants and products GF will serve and how many good units it can actually supply.
Beyond that, it will be necessary to confirm that the supplied interposers are combined with compute chips and HBM, go through package assembly and testing, and ship as finished products. The start of operations at a component manufacturing site alone does not mean AI chip shipment volumes have increased.
The agreement also does not clarify where HBM and package substrates will be sourced. Even if compute chips and silicon interposers can be manufactured in the US, that alone does not mean every component needed for the finished product can be procured domestically.
To evaluate how far the US supply chain has come together, it is necessary to check not only where manufacturing sites are located but also the sourcing of each component and the production capacity of each process.
If the interposers GF manufactures and US advanced packaging facilities are used for volume production of the same products, and the necessary HBM and substrates can also be sourced reliably, TSMC's customers will be able to choose the US not only for manufacturing compute chips but also for the processes that complete AI chips.
The significance of this $2 billion agreement lies not only in establishing a new manufacturing site in the US, but in whether it can help build a supply system that connects front-end and back-end processes and actually ships AI chips. The results will become clear after 2028, when GF's volume production ramp-up begins.