SK hynix is advancing the introduction of AI agents into semiconductor mass-production equipment. The Elec reported on August 13, 2026 that the company is gradually testing functions for configuring and operating equipment on back-end lines in Cheongju. At Samsung Electronics as well, verification of a customer-specific SoC using Claude Code shrank from an expected month-plus to two days. As AI moves beyond finding and answering from documents into processes that affect yield and post-production quality, how to prevent malfunctions while accelerating work has become a shared challenge for design and manufacturing alike.
SK hynix to measure reliability in back-end processes through year-end
According to The Elec, SK hynix is gradually introducing AI agents into semiconductor back-end process lines in Cheongju, verifying the equipment's production performance as well as the effectiveness and reliability of the AI functions. The target equipment and products have not been disclosed. The evaluation is expected to conclude by the end of 2026.
In back-end processes, wafers that have completed front-end processing are assembled into products and tested to confirm they meet customer requirements. Conventional rule-based automation operates equipment according to conditions and thresholds set by engineers. AI agents, by contrast, configure equipment functions in response to the situation, aiming to shorten process time and reduce variation among individual workers. Because the scope of judgment widens, reproducibility in a mass-production environment and how to halt operations upon failure must be confirmed beforehand.
The Elec reports that the rollout has also been incorporated into on-site performance evaluation systems. The KPIs of employees responsible for equipment certification are now tied to the success of verifying and deploying AI software, and yield improvements achieved through AI are also reflected in personnel evaluations. However, the magnitude of yield improvement and the malfunction rate during testing have not been disclosed. What will be confirmed at year-end is not the number of deployments, but whether the technology has reached a level at which it can be entrusted with mass-production equipment.
Computing infrastructure is also moving closer to the factory floor. In April, The Elec reported that SK hynix had completed procurement of 250 AI servers and 2,000 NVIDIA Blackwell GPUs for Cheongju, with delivery and installation to begin in June. SK Telecom completed a pilot in 2025 of a digital twin that replicates SK hynix's fab in virtual space. An environment where the effects of process changes and equipment layout can be tested in virtual space before implementation, combined with on-site AI infrastructure, is a prerequisite for connecting agents to mass-production lines.
Verifying 64 data paths before actual RTL is complete
Samsung's case occurred not in manufacturing equipment but in design verification for a customer-specific SoC. According to Chosun Biz, the System LSI division opened Claude Code to software developers in advance in May 2026. About three months later, the team completed the construction and verification of a test environment—work expected to take over a month—in two days, internally assessing that the work had sped up roughly 15-fold.
The target was an SoC involving 64 data paths, a project combining a new chip architecture with design assets from an external company. Some standardized design documentation was missing, and the DRAM controller's RTL did not arrive by the scheduled date. RTL is design information describing the behavior of digital circuits and data flow, and is normally a prerequisite for completing a verification environment.
Using Claude, the AI determined IP placement and connections from available SoC information, internal communication standards, and verification IP from an EDA company. It further built a virtual verification environment and test scenarios, connecting a virtual block in place of the unfinished DRAM controller portion. This allowed the team to examine key data paths and find early errors before the actual RTL arrived.
The figure of two days is the result of one project carried out under these specific conditions. It's not that the entire SoC design process became 15 times faster—what was shortened was the construction and verification of the test environment. Even so, there is novelty in changing the sequence of waiting for upstream deliverables before starting work, and in virtualizing unfinished portions to enable parallel verification.
From a 50% cut in design time to agents connecting processes
At NVIDIA GTC 2026 in March, Samsung announced it had cut the time required for AI-assisted analog/logic design by approximately 50%. Using reinforcement learning and genetic algorithms, the company automated the adjustment of transistor dimensions and predicted design rule violations before layout. According to the official explanation, this optimization also contributed to achieving up to 13Gbps per pin in HBM4.
In July, another result of applying AI to memory design was presented. Jung-yeon Choi, Vice President of Samsung's Memory Division, explained in a lecture at the semiconductor engineering society that a Neural Compact Model reduced by more than 95% the time needed to re-adjust the PDK in response to process changes. A PDK is reference data used to reflect the characteristics of a manufacturing process in circuit design. An agent that quickly checks whether the critical path meets target performance under a revised PDK has also been under development and trial use since early 2026.
The 50% and 95%-plus figures cannot be directly compared, since they measure different types of work. What they have in common is that AI's role is expanding from automating individual tasks to a mechanism that passes results between schematics, layout, and manufacturing data. Samsung is building a multi-agent workflow in which an agent handling schematics predicts downstream performance, power consumption, and area, while the layout side reflects updates to the schematic.
Before speed, a design that can be stopped is needed
A failure case at Samsung reported by Chosun Biz illustrates the difficulty of using agents in semiconductors. When instructed to fix an error, the AI, instead of correcting the root cause, changed the error message to generic information. When asked to revert a specific function, it rolled back other completed work as well, and when asked to analyze verification results, it reportedly attempted to alter the actual RTL. None of these cases resulted in product defects, but they show that plausible-looking output alone cannot pass verification.
The factory floor imposes other constraints as well. Semiconductor fabs are isolated from external networks to protect confidential information, requiring computing infrastructure that runs AI either within equipment or on-site. Choi cited legal protection of design data and rising infrastructure costs—including GPUs and CPUs—as challenges. The Elec has also reported that embedding high-performance GPUs into manufacturing equipment would push up equipment prices.
Even so, the scope of adoption is expanding. The Elec reports that Samsung has begun requiring equipment makers to build AI agents as a standard feature into newly ordered manufacturing equipment. If software that factories previously added after the fact becomes instead a condition of equipment purchase, then agent performance and maintenance systems will also become criteria for equipment selection.
SK hynix has set a goal of an "Autonomous Fab" by 2030 and has established a dedicated organization and a joint-development structure with partners. Samsung, too, is expanding the scope of application while humans specify the range of tasks and re-verify AI outputs. How much of the previously undisclosed target equipment and reliability standards will be revealed in SK hynix's year-end evaluation will be the first milestone in gauging whether AI agents can move from pilot deployment to standard equipment in mass production.