Details have emerged about Verano, the CPU AMD will use in its next-generation AI rack, Helios 500. It comes in a 72-core configuration based on Zen 6 and a 192-core configuration based on Zen 6c, and its theoretical peak LPDDR5X memory bandwidth is expected to be about 800GB/s. NVIDIA's competing Vera offers up to 1.2TB/s of memory bandwidth, so Verano reaches only about two-thirds of that. However, the two companies' CPUs differ in both core count and intended use, so memory bandwidth alone cannot settle which is better. What stands out about Verano is that, rather than maximizing the CPU's standalone memory performance, it appears to prioritize high-speed connectivity with the GPU and power efficiency.
Verano is a CPU optimized for GPU racks
In an announcement on July 23, 2026, AMD said Helios 500 will use Instinct MI500 series GPUs and the EPYC "Verano" CPU. The MI500 series is scheduled for 2027, and Helios 500 will also be paired with the next-generation Pensando networking products "Como" and "Monza." The current Helios consists of 72 Instinct MI455X GPUs and 18 EPYC "Venice" CPUs, and Verano will serve as the successor generation. At a technical briefing on November 10, AMD also disclosed further details of Verano and said shipments will begin in the second half of 2027.
Verano is a Zen 6-generation CPU like Venice, which targets general-purpose servers, but its configuration is quite different. The package carries six CPU core complex dies (CCDs) and two I/O dies, and runs at up to 5.3GHz in the 72-core Zen 6 configuration and up to 4.1GHz in the 192-core Zen 6c configuration. According to ComputerBase, the package also includes two dummy dies to even out its physical layout. Unlike Venice SP7, which supports up to 256 cores, Verano keeps the core count lower while optimizing its memory and GPU connectivity for racks.
For memory, it uses low-power LPDDR5X rather than the conventional server DDR5 RDIMM or MRDIMM. Four memory controllers across the two I/O dies support a 24-channel configuration at up to 8,533MT/s. The memory is implemented as replaceable SOCAMM2 modules, while Verano itself is a BGA package soldered directly to the board rather than seated in a socket. In The Register's November 10 report, AMD's Madhu Rangarajan explained that BGA mounting was chosen on the CPU side because LPDDR5X requires limiting the signal-quality degradation caused by connectors.
This design has implications for both power efficiency and serviceability. In its technical explanation of LPDDR5X and SOCAMM2, AMD says that combining low-power memory with replaceable modules can deliver both energy savings and serviceability in servers. SOCAMM2 is more compact than a typical DIMM and mounts horizontally to the board, which is also advantageous for cooling design. However, even though the memory modules can be swapped, the CPU itself is soldered to the board, so replacing the CPU alone is difficult.
Regarding Verano's development approach, Rangarajan told The Register that it is designed for rack-scale systems that integrate CPUs and GPUs. He also said its competitor is not the standalone Vera CPU but the entire system combining Verano with GPUs, positioning it against NVIDIA's Vera Rubin. Indeed, NVIDIA deploys Vera not only as a GPU host but also in standalone CPU servers that handle AI agent workloads, data analytics, and more. Verano, by contrast, is a product focused on running Instinct GPUs efficiently.
Per-core memory bandwidth is about 31–81% of Vera's
Verano's theoretical peak memory bandwidth is put at about 800GB/s. According to NVIDIA's official technical documentation, Vera has 88 custom-designed "Olympus" cores and up to 1.2TB/s of bandwidth with LPDDR5X memory. In terms of total CPU memory bandwidth, Verano is about 67% of Vera, but once core counts are taken into account, the gap widens depending on the configuration.
| CPU | Cores | Theoretical peak memory bandwidth | Bandwidth per core | vs. Vera |
|---|---|---|---|---|
| AMD Verano (Zen 6) | 72 | ~800GB/s | ~11.1GB/s | ~81% |
| AMD Verano (Zen 6c) | 192 | ~800GB/s | ~4.2GB/s | ~31% |
| NVIDIA Vera | 88 | Up to 1,200GB/s | ~13.6GB/s | 100% |
Note: Verano's bandwidth is a reported figure; Vera's is NVIDIA's stated maximum. Both are simple calculations dividing per-CPU theoretical peak bandwidth by the number of physical cores, and do not represent measured performance.
In the 72-core Verano, dividing about 800GB/s by 72 gives roughly 11.1GB/s per core. In the 192-core configuration it falls to about 4.2GB/s, only about 31% of Vera's roughly 13.6GB/s. This suggests that when many CPU cores access memory simultaneously, the 192-core configuration may be more prone to bandwidth contention. However, CPU processing speed also depends on cache efficiency, memory access frequency, compute performance, and other factors, so per-core bandwidth at 31% does not mean performance is 31% of Vera's.
Comparing Verano with the existing Venice also requires considering differences in memory configuration. According to specifications released by AMD, Venice SP7 has a maximum memory bandwidth of about 1.6TB/s with MRDIMMs, so Verano's roughly 800GB/s is half of that. But Venice SP8's maximum bandwidth is about 819GB/s, nearly the same as Verano. Verano therefore has not simply halved memory bandwidth relative to every Venice product; it is better understood as a different design choice from SP7, which emphasizes maximum bandwidth.
One reason Verano adopted LPDDR5X is to reduce memory power consumption. According to The Register, AMD says it can cut memory power by about 30–40% compared with conventional RDIMMs. The design appears to prioritize making effective use of the whole GPU rack's power budget over maximizing the CPU's own memory bandwidth. That is consistent with AMD's stated policy, in its official blog, of optimizing performance per watt across the entire AI rack.
Memory bandwidth is held down, but GPU connectivity gets faster
Verano also changes the interconnect between CPU and GPU. According to The Register, AMD's xGMI (a high-speed chip-to-chip link that uses Infinity Fabric) rises from 64Gbps per lane in Venice to 112Gbps in Verano. That is a 1.75x increase in per-lane signaling speed, indicating a design aimed at faster data transfer with the GPU. As for Verano's PCI Express connectivity, PC Watch, citing AMD's technical briefing materials, reports that it has 96 lanes of PCIe 6.0.
The Register suggests AMD may have changed the memory controller configuration and redirected I/O die circuit area toward high-speed SerDes (serializers/deserializers). This is an inference from the disclosed configuration; AMD has not specifically explained how it allocated circuit area. Even so, the fact that Verano raises xGMI signaling speed while holding memory bandwidth below SP7 hints at a design that emphasizes communication with the GPU rather than just the CPU's internal memory handling.
That said, even with a 1.75x per-lane speedup, total CPU-GPU bandwidth will not necessarily grow by the same proportion. Actual bandwidth depends on the number of links, what they connect to, transmission efficiency, and so on. NVIDIA uses second-generation NVLink-C2C between Vera and Rubin GPUs, and in its official announcement states up to 1.8TB/s of coherent CPU-GPU bandwidth. AMD has not disclosed how many links will connect Verano to GPUs, so it is not yet possible to judge which side has the bandwidth advantage over Vera Rubin.
The CPU-to-GPU ratio also matters. The current Helios pairs one CPU with four GPUs, whereas Vera Rubin NVL72 has 36 CPUs and 72 GPUs, or two GPUs per CPU. The Register estimates that if Verano were configured with one CPU per two GPUs, it might achieve chip-to-chip bandwidth comparable to Vera Rubin, while at the same 1:4 ratio as the current Helios, per-GPU bandwidth could be only about 448GB/s. However, these figures are estimates based on an assumed connection configuration, not confirmed Verano specifications.
Challenges remain in power efficiency and serviceability
Verano's adoption of LPDDR5X relates not only to bandwidth and power consumption but also to system reliability. In its official technical explanation of SOCAMM2, AMD notes that LPDDR5X-based memory modules have RAS (reliability, availability, serviceability) features that are not yet as mature as those of conventional server RDIMMs. In particular, for servers expected to run continuously for long periods, the gap with RDIMM capabilities in error correction and continued operation during failures needs to be closed. AMD indicates that, for the time being, LPDDR5X adoption may center on uses where fault tolerance can be ensured on the software side.
On the maintenance side, BGA mounting of the CPU is also an operational constraint. Replaceable SOCAMM2 memory makes handling failures easier, but because the CPU is fixed to the board, the situation differs from typical servers where the CPU alone is swapped out upon failure or generational upgrades. When procuring AI racks, buyers will need to evaluate not only CPU specifications but also board-level replacement costs, maintenance contracts, and compatibility with cooling infrastructure. A design that optimizes CPU and GPU together may be advantageous for performance and power efficiency, but it also limits operational flexibility.
Verano's 2027 final specifications will shape how it is judged
The first thing to check in assessing Verano's performance is the memory bandwidth at shipment. The roughly 800GB/s currently reported is a theoretical peak assuming LPDDR5X-8533, and AMD says there is room to raise memory speed before shipping. If bandwidth in the 72-core configuration rose to about 982GB/s, it would come to about 13.6GB/s per core, matching Vera's stated figure on paper. In the 192-core configuration, however, even the same bandwidth would be only about 5.1GB/s per core, so the differences between configurations remain large.
Still, it is not appropriate to evaluate Verano's design on per-core memory bandwidth alone. A GPU host CPU has many roles, including preprocessing data, transferring it to the GPU, and managing communication and jobs. Actual system performance depends on a combination of factors: not just CPU memory bandwidth but also GPU connection bandwidth, transfer latency, memory capacity, CPU processing performance, and how software divides the work. Because Vera and Verano also differ in their intended uses, comparing them requires evaluation with equivalent GPU configurations and workloads.
Another point to watch is the CPU-to-GPU ratio adopted in Helios 500. Although it has been reported that Verano's xGMI is faster than Venice's, the effective bandwidth allocated to each GPU will vary with the rack configuration. Even if CPU-GPU bandwidth at shipment falls short of Vera Rubin, that alone would not negate the view that AMD has shifted the design from Venice toward emphasizing GPU connectivity. However, claiming a connectivity advantage over competing products would require confirming the actual link configuration and total bandwidth.
AMD positions Verano not as a simple successor to general-purpose server CPUs but as a dedicated CPU for AI racks that operates as one with Instinct GPUs. The power-efficiency gains from LPDDR5X and the faster xGMI give concrete form to that design philosophy. Ahead of the launch planned for the second half of 2027, attention will be on whether the final memory bandwidth and GPU connectivity specifications, along with rack-level performance, power consumption, and maintenance terms, are made clear.