Finding small flakes of molybdenum disulfide (MoS₂) from microscope images, determining their thickness, and drawing electrodes to match their position—a joint team from KAIST, the Ulsan National Institute of Science and Technology (UNIST), and others has published research automating this entire workflow. From over 120,000 candidates, they fabricated and measured 1,615 field-effect transistors (FETs), statistically capturing how thicknesses ranging from 3 to 8 layers affect current flow and switching performance.
The core achievement here isn't a new AI accelerator or a mass-production process. Rather, it lies in connecting to data processing the workflow of "finding materials, turning them into devices, and comparing them under the same conditions"—work that had previously relied on researchers' eyes and hands. If this brings us closer to low-power AI chips, it's because it enables testing vast numbers of candidate materials and generating data—complete with variability—that can be used for circuit design.
The research paper was published online in Advanced Functional Materials on April 3, 2026. KAIST announced the research on July 9.
From "Finding" 120,000 Flakes to "Wiring" Them
MoS₂ flakes created via exfoliation land at unpredictable locations on the substrate. Their size, orientation, and thickness vary, and some flakes contain wrinkles, folds, overlaps, or residue. Conventionally, researchers would peer through a microscope to select usable flakes and then design source-drain electrodes to match their coordinates and shape. While feasible for a small number of devices, this approach was too burdensome for collecting sufficient samples across different layer counts.
The research team captured optical microscope images, corrected for uneven illumination and lens-edge darkening, and then extracted contours. After excluding tiny detections under 500 pixels and regions with distorted shapes, they recorded each flake's RGB brightness, orientation, dimensions, surface condition, and absolute coordinates on the substrate. They further automated layout generation, rotating electrodes to match each flake's angle and wiring them out to peripheral terminal pads.
On a representative 1.5×1.5cm substrate, they detected 74,119 flakes and narrowed these down to 403 with uniform surfaces suitable for device placement. Across the entire study, they classified over 120,000 flakes and electrically evaluated 1,615 FETs. These numbers shouldn't be misread: they didn't fabricate 120,000 transistors, but rather selected fabricable flakes from a vast pool of material candidates and connected them to device data at the thousand scale.
Distinguishing 3 to 8 Layers by Light and Dark
With each additional atomic layer, MoS₂'s optical contrast against the substrate changes. The team primarily used red and green brightness as clues, removing outliers via density-based DBSCAN clustering, then classified flakes into six groups using a Gaussian mixture model. Since the outer 20% of a flake's perimeter tends to pick up contour irregularities, they excluded this region and evaluated brightness only within the inner 80%. Flakes with blurred images or localized folds show broadened brightness distributions, allowing them to be filtered out at this stage.
Layer count wasn't determined by optical measurement alone. Atomic force microscopy (AFM) measured the thicknesses of the six groups as 2.05, 2.72, 3.26, 3.80, 4.26, and 4.75nm. Converting using 0.65nm per MoS₂ monolayer, these correspond to 3 to 8 layers. Raman spectroscopy also confirmed that the spacing between two vibrational modes changes according to layer count.
This method worked across substrates of varying thickness and material—aluminum oxide, hafnium oxide, and silicon oxide. Beyond electrochemically exfoliated flakes, the team also detected MoS₂ grown via metal-organic chemical vapor deposition (MOCVD). However, optical response varies with material, substrate, and lighting conditions. Applying this method to other 2D materials would require recalibrating the correspondence between optical signals and layer count using AFM or spectroscopy.
Thicker Layers Flow Better But Switch Worse
What large-scale measurement revealed is that there's no single "best" thickness. As MoS₂ thickness increased from 3 to 8 layers, on-current increased and contact resistance with metal electrodes decreased. On the thicker side, charge injection from metal electrodes into the channel became easier.
The tradeoff was weaker gate control over the entire channel. Off-state leakage current increased, and subthreshold swing also worsened. Subthreshold swing indicates the gate voltage change required to switch a transistor from off to on—smaller values mean sharper switching at lower voltages. Thin channels are easier to control electrostatically but harder to inject charge into from contacts. Thick channels show the opposite behavior.
The paper explains this shift as a transition from a regime dominated by electrostatic control on the thin side to one limited by charge injection on the thick side. For low-power circuit design, maximizing on-current alone isn't sufficient. Standby leakage, operating voltage, and power lost at contacts must all be compared on the same dataset, with layer count selected according to the intended application.
The Path to AI Chips Depends on Whether Device Data Can Be Handed Off to Circuits
The FETs in this study are research-grade devices with a 3µm channel length, far from the dimensions of cutting-edge logic. This is not research that prototyped an AI processor using MoS₂. Even so, the 1,615-device dataset organized by layer count holds value distinct from record-setting single devices. With median values, distributions, contact resistance, threshold voltage, and leakage current relationships all in place, compact models incorporating thickness and device variability can be built and handed off to circuit simulation.
Much work remains before this reaches manufacturing. While 2D transistors, being atomically thin, can suppress short-channel effects, barriers formed at metal contacts impede current flow. Processes are needed to grow high-quality films over large areas and transfer them onto existing wafers without damage. Furthermore, gate dielectrics and self-aligned processes must be developed, and p-type FETs must also be established—none of this yet constitutes a CMOS circuit. This automation effort doesn't solve these problems; rather, it provides a tool for measuring results at scale and under consistent standards when conditions are varied.
The next test is clear: does layer-count determination and automated wiring continue to function when channels and contacts are scaled down to the nanometer regime, and does it reproduce across different materials and fabrication batches? Furthermore, can measurement data be converted into a publishable format, and can device models predict the power and speed of actual circuits? Only once these milestones are reached can we say that automated microscope image processing has shortened the design timeline for low-power AI chips.