In a notice dated September 4, Chinese test equipment maker Seichi Tech (精智達) announced that it had signed a contract to sell semiconductor test equipment and fixtures. The total contract value is RMB 1,576.35 million including tax, based on the purchase quantities its customer expects. The actual quantities and amounts may change depending on the orders eventually placed.
Seichi's memory chip test equipment business posted a 147.05% year-on-year increase in sales in the first half of 2026. Growing demand for AI memory is creating an opportunity for expansion among Chinese test equipment makers as well.
However, order values and sales growth alone do not show how far these companies can replace foreign-made equipment in HBM mass-production lines. Sorting public product specifications and contract details by test stage shows how far Chinese makers have advanced technologically, and what needs to be checked to judge their readiness for HBM.
The memory tester market is forecast at $2.5–3 billion
Seichi's growth is supported by rising demand for equipment that electrically tests memory, from conventional DRAM to high-bandwidth memory (HBM).
According to the company's first-half results summary, companywide revenue was RMB 804 million, up 81.17% year on year. The 147.05% growth rate applies only to the memory chip test equipment business within the company. Because Seichi also makes test equipment for displays, its total revenue cannot be treated as memory-related sales.
The global market is also expected to expand. In its July 29 earnings presentation, Advantest forecast the 2026 memory tester market at $2.5–3 billion. That is raised from $2.2–2.7 billion as of April, as growing investment in high-performance DRAM spills over into the test equipment market.
On page 18 of its April 27 materials, Advantest estimated the 2025 global memory tester market at $2.1 billion, with its own share at 61%. Against incumbents with large global sales, the competitive question is which test stages Chinese companies can enter first.
Companywide revenue growth, market sales share, and the proportion of equipment actually adopted in semiconductor fabs need to be considered separately, because each measures something different.
Why HBM needs more testing capacity, not just more output
HBM is made by stacking multiple DRAM dies. If defective dies cannot be weeded out before stacking, the cost invested in the other dies and in the stacking and bonding processes can be lost once a bad die is built in. That is why wafer-level testing to select known good dies before stacking is important.
But testing does not end there.
Page 16 of Advantest's 2023 technical briefing shows a flow in which DRAM and logic wafers are each tested, and memory cells and functions are tested several more times after stacking.
The actual sequence varies by product and manufacturing method, but the pre-stacking selection of good dies and the post-stacking operational checks play different roles. Even a die judged good before stacking can develop new defects during stacking and interconnect processes.
The factors driving test equipment demand are not limited to production volume. As memory capacity and the number of stacked layers increase, there are more memory cells and test items to examine, and test time per device grows.
Meanwhile, higher power consumption and heat at high operating speeds make it harder to test many chips at once. Advantest's materials likewise cite longer test times and limits on parallel measurement counts as challenges.
Leaving aside changeover and downtime, the number of chips that can be tested per unit of time can be roughly thought of as parallel test count divided by test time. If test time per device lengthens and the number that can be measured simultaneously is also constrained, more test capacity is needed even to process the same output.
This is why test equipment demand cannot be calculated as a simple proportion of HBM production volume.
From burn-in to final test: how far does Chinese equipment reach?
Seichi offers products for several memory test stages. Based on product names and functions on its official pages as of October 5, 2026, the stages they handle can be organized as follows.
| Seichi model | Main test stage | Published speed | Published parallel test count |
|---|---|---|---|
| S9620 | DDR/LPDDR burn-in and core testing | Up to 100MHz / 200Mbps | 23,040 DUT in total |
| S9930 | DRAM wafer testing and repair | 200MHz / 400Mbps in the feature table; expandable to 1.125GHz / 2.25Gbps | 2,048 DUT per TD (as stated in the original) |
| S9880 | High-speed final test of DRAM | Up to 9Gbps | 768 for DDR4/5, 384 for LPDDR4, 192 DUT for LPDDR5 |
According to Seichi's published specifications, the S9620 handles burn-in, the S9930 wafer testing, and the S9880 final testing, each serving a different purpose.
DUT in the table stands for "Device Under Test," meaning the chip being tested. "TD" for the S9930 is not defined on the official page, so its relationship to how many chips the whole system can measure simultaneously cannot be confirmed.
The speeds and parallel counts are also figures given under different conditions for different memory types and test stages. The table cannot be read as a performance ranking of the three models.
Burn-in is a test that applies temperature and electrical stress to find latent defects that are unlikely to show up in normal operation. The S9620 supports test temperatures of −10 to 150°C and uses a configuration that tests many chips at once.
By contrast, for the S9880, which tests finished devices at high speed, maximum operating speed and supported memory types matter. Equipment that processes large numbers of chips in parallel and equipment that verifies high-speed operation prioritize different performance characteristics.
The S9930's speed figure also calls for caution. The official page advertises up to 2.25Gbps, while the product feature table says it is expandable from 400Mbps to 2.25Gbps. The 2.25Gbps figure therefore cannot be assumed to be available in every configuration currently shipped.
In addition, these pages mainly present product specifications for DDR and LPDDR, and are not evidence of adoption in HBM mass production.
Still, they show that when considering substitution with Chinese equipment, it is necessary to think by process, such as burn-in, wafer testing, and final testing, rather than treating a finished HBM stack as a single unit. To track the progress of Chinese makers, one first has to distinguish which test stages they can actually handle.
What Korean cases show about the gap between published specs and mass-production adoption
New makers entering through specific test stages can also be seen in Korean HBM manufacturing.
In an August 26 exclusive, Korea's ETNews, citing industry sources, reported that Digital Frontier and UniTest together received orders worth KRW 283.94 billion in 2026 for HBM4 wafer-test-related equipment for SK hynix. According to the paper, Korean makers are entering by handling specific test functions, complementing the existing supply structure.
UniTest also says it completed, early in the year, the qualification evaluation required for introducing its HBM4 burn-in equipment into mass-production lines.
This is not an example of adoption by a Chinese maker. But it helps illustrate that the stage at which an equipment maker publishes product specifications is separate from the stage at which it passes evaluation for use in a chipmaker's mass-production line.
Moreover, preparing the tester itself is not enough to make wafer testing work. A probe card is needed to deliver the electrical signals generated by the tester to the chip.
In its official explanation of high-speed known-good-die testing, FormFactor cites, in addition to high-speed signal quality, contact position shifts caused by temperature changes as a challenge.
Because probe cards and wafers expand thermally in different ways, aligning the contacts becomes harder when temperature changes. Even if high-speed electrical signals can be sent accurately, testing fails if stable contact with the intended terminals cannot be made.
To make HBM test equipment procurable within China, the entire test system, including not only the tester itself but also contact components such as probe cards and temperature control, must be made to run stably under actual mass-production conditions.
A large contract and 18Gbps development: mass-production adoption is still needed
Seichi's push toward higher speeds is also evident from its explanation of first-half results. The company says the main technical indicators of its 18Gbps high-speed final test equipment have reached their intended targets.
However, this announcement alone does not show that equipment supporting a specific HBM generation has been adopted in a customer's mass-production line and passed acceptance.
Even at the same maximum speed, overall equipment performance is not necessarily equivalent.
Advantest's T5503HS2 also lists a maximum of 9Gbps, but states an overall timing accuracy of ±45ps. The 1ps figure for Seichi's S9880, meanwhile, is "edge resolution," which indicates how finely signal timing can be set.
The increment of time that can be set and the accuracy, which shows how far the actual signal deviates from the intended time, are different metrics. It is therefore not possible to simply compare 1ps with ±45ps and judge which equipment performs better.
Comparing real performance requires aligning the target memory, test content, electrical conditions, and so on.
The large contract mentioned at the outset also does not reveal how far it extends to HBM mass production.
In the September 4 contract notice, the customer name, product specifications and model numbers, quantities, and unit prices are withheld as business secrets. The total contract value is calculated from the quantities the customer expects to buy, and the actual quantities and amounts may change with actual orders.
Delivery is scheduled within two years, and the contract is expected to contribute to sales in 2026–2028 as it is fulfilled.
The RMB 1,576.35 million is therefore an expected total under the contract, not an amount already booked as revenue for the period. Nor can the published materials be used to work out how much of the contract value corresponds to HBM test equipment.
Growing orders and a broader product lineup show that Chinese makers, including Seichi, are expanding their semiconductor test equipment businesses.
What will matter in judging progress from here are the memory generations supported, the test stages actually handled, passing customers' mass-production evaluations, and whether equipment continues to be adopted after delivery.
Can these makers meet the speed, accuracy, throughput, and stability required at each stage and accumulate adoption in mass-production lines? That will determine how far equipment demand from rising HBM output translates into growth for Chinese makers, and how much dependence on foreign-made test equipment can be reduced.