China's ChangXin Memory Technologies (CXMT) is closing in on Micron in terms of DRAM wafer input capacity. SemiAnalysis estimates that CXMT will reach 350,000 wafers per month by the end of 2026, representing 90.9% of Micron's 385,000 wafers per month. However, the number of wafers fed into a fab is not the same as the quantity or value of memory that can be extracted from them. To gauge the pressure CXMT's capacity expansion places on the three major memory makers, one must look beyond wafer counts to bit shipment volumes and product mix.
The Gap Between 350,000 and 385,000 Wafers per Month
SemiAnalysis estimates CXMT's DRAM wafer input capacity at the end of 2026 will be 350,000 wafers per month (WSPM), compared to approximately 385,000 for Micron. The difference is 35,000 wafers per month, putting CXMT at 90.9% of Micron's level. When comparing monthly fab scale alone, the gap between the two companies has narrowed considerably.
According to the same SemiAnalysis estimates, Samsung Electronics stands at 720,000 wafers per month and SK hynix at 595,000. CXMT still trails these two significantly, but in terms of wafer capacity, it is closing in on Micron—currently the world's third-largest—and solidifying its position as the fourth-largest. This represents an increase of 85,000 wafers per month over the course of a year, up from 265,000 WSPM at the end of 2025.
WSPM here refers to the number of 300mm wafers that can be fed into front-end processing per month. It does not represent the number of completed DRAM chips, nor does it reflect the aggregate bit capacity of shipped products. Still, because it allows for an apples-to-apples comparison of fab scale—including manufacturing equipment, cleanrooms, and personnel—it serves as a meaningful measure of the entry point into supply capability.
Three Fabs and DDR5: CXMT's Current Standing
CXMT already has fabs in operation and products on the market. According to listing-related documents filed with the Shanghai Stock Exchange, the company operates a total of three 12-inch DRAM fabs across Hefei and Beijing. Omdia data shows CXMT ranks first in China and fourth globally in both shipment volume and revenue, and it has already moved its fourth-generation process node into mass production.
The company's product generation has advanced from DDR4 to DDR5. CXMT offers 16Gb and 24Gb DDR5 chips with maximum speeds exceeding 8000Mbps, and has also unveiled a lineup of modules including server-oriented RDIMMs and MRDIMMs. In LPDDR5X, the company moved 8533Mbps and 9600Mbps products into mass production in May 2025, and has begun sample shipments of a 10667Mbps product to customers.
According to the listing documents, 2025 revenue by product category showed LPDDR at RMB 40.70355 billion (66.43%) and DDR at RMB 19.53129 billion (31.87%). Commodity DRAM for mobile devices such as smartphones, PCs, and servers accounts for nearly the entirety of the company's business. CXMT has a product lineup and customer base supporting its current production, but it remains unclear how quickly the company can translate its capacity additions into actual shipments.
The Same 350,000 Wafers, Different Effective Bit Output
At the same time, reaching 350,000 wafers per month does not guarantee CXMT will produce the same volume of memory as Micron. The effective bit yield per wafer depends on die area, capacity per die, yield rate, and fab utilization. As process nodes advance and more bits can be packed into the same die area, the same wafer count can yield more shippable memory.
SemiAnalysis considers CXMT's primary 2026 process node to be G4, roughly equivalent to the industry's 1z generation. The firm estimates CXMT's per-bit manufacturing cost for DDR5 is more than 30% higher than that of the three major memory makers. SemiAnalysis also projects CXMT's global bit shipment share will rise only modestly, from 9% in 2025 to 12% in 2027—far slower growth than its wafer capacity ratio would suggest.
There are also differences in product allocation. SemiAnalysis expects CXMT to increase capacity allocated to HBM from 5,000 wafers per month at the end of 2025 to 30,000 wafers per month by the end of 2026, but this still falls short of 10% of total capacity. Micron, meanwhile, has already begun mass shipment of HBM4 using its 1β process, and is preparing for 2027 mass production of HBM4E using its EUV-based 1γ process. In HBM for AI accelerators, a substantial gap remains between the two companies in terms of revenue generated and strategic value per wafer.
DUV Multi-Patterning and Export Controls
For CXMT to advance to next-generation process nodes, it must solve both lithography and yield challenges simultaneously. Even fabs without access to EUV equipment can continue shrinking feature sizes by exposing the same layer multiple times using 193nm immersion DUV. However, this approach also increases the number of deposition and etching steps in addition to exposure, lengthening the overall process. According to an imec model presented by ASML, single EUV exposure reduces the number of process steps per wafer by roughly 20% compared to DUV multi-patterning.
Whether CXMT can secure sufficient equipment also remains uncertain. In 2022, the U.S. Department of Commerce's Bureau of Industry and Security (BIS) introduced a licensing requirement covering equipment exports and support by U.S. persons for Chinese fabs capable of manufacturing DRAM at half-pitch below 18nm. BIS has since revised its definition of advanced DRAM miniaturization. Under current export control regulations, advanced DRAM is defined by any of the following criteria: memory cell area below 0.0026 square micrometers, density exceeding 0.20Gb per square millimeter, or more than 3,000 through-silicon vias per die.
The regulations do not uniformly ban all DUV equipment. Nonetheless, because licenses are required for equipment and technical support related to advanced DRAM, expanding capacity, performing maintenance, and transitioning process nodes all become more difficult. Even once a fab building is complete, WSPM does not translate into actual shipment volume unless the necessary number of lithography tools can be installed, the process stabilized, and operations sustained at the quality level customers demand.
Will Increased Capacity Lower PC Memory Prices?
SemiAnalysis forecasts that CXMT's wafer input capacity will grow to 420,000 wafers per month by the end of 2027 and 500,000 by the end of 2028. Bit shipment share is expected to rise from 9% in 2025 to 12% in 2027. As more suppliers of commodity DRAM enter the market, China's dependence on the three major memory makers for smartphones, PCs, and servers is likely to decrease, potentially freeing up more supply for other regions.
However, SemiAnalysis predicts that even accounting for CXMT's capacity expansion, DRAM shortages will persist through 2028, and Micron has similarly indicated that supply-demand tightness will extend beyond 2027. Even as new wafer capacity comes online, demand for HBM and high-capacity DRAM for AI servers continues to grow. It seems unlikely that 350,000 wafers per month alone would immediately trigger a collapse in PC memory prices.
Whether actual input volume reaches 350,000 wafers per month by year-end, and whether bit shipment share climbs to 12% by 2027, remain to be seen. The yield of next-generation process nodes and progress on the 30,000 wafers per month allocated to HBM will also need to be verified individually. How close CXMT truly gets to Micron will be determined not by fab floor space, but by how many good bits it can produce from each wafer.