On October 10, Cao Kanyu, president of China's leading DRAM maker CXMT (ChangXin Memory Technologies), announced at the 4th Integrated Circuit and Chiplet Conference in Shanghai that the company plans to launch next-generation DDR5 RDIMMs by the end of 2026. The modules will combine a new "4F²" architecture with hybrid bonding technology. RDIMMs are registered memory modules used mainly in servers. The announcement included no concrete specifications, such as process generation, data transfer speed, or capacity. Even so, three days later, on October 13, SK hynix shares fell 10.09% in the Korean market, and the KOSPI index dropped 5.46%.
The technological catch-up by a Chinese manufacturer heightened market concerns, but key information is still missing for judging whether CXMT can actually pull ahead of its rivals. Of particular note is the process scaling level, which was not disclosed. If you estimate cell area using the manufacturing dimensions assumed by analysts and the figures CXMT published in September for a different DRAM platform, the advantage over competitors reverses depending on the assumptions. However, these numbers do not necessarily represent the same dimension, so the results cannot be taken as an actual difference in technological capability.
CXMT's 4F² Technology and the Product Specs That Were Not Disclosed
In his October 10 talk, Cao Kanyu introduced a 4F² architecture centered on CXMT's in-house developed "VSG (Vertical Surrounded Gate)" transistor. The VSG is a transistor structure in which the channel carrying the current is arranged vertically and surrounded by the gate. It aims to strengthen gate control over the current compared with conventional structures, suppressing leakage current and short-channel effects while reducing the footprint of the memory cell. According to a TrendForce report published on October 12, CXMT also said it holds more than 300 published patent families related to 4F², among the largest portfolios in the industry. This is the company's own claim, however, and no comprehensive third-party comparison has been presented.
The main points revealed in the talk were the 4F² architecture, the VSG transistor, more than 300 published patent families, and the plan to launch DDR5 RDIMMs by the end of 2026. On the other hand, the specific process generation, data transfer speed, DRAM die capacity, module capacity, manufacturing yield, shipment volume, and customer qualification status have not been disclosed. The exact launch date is also unclear, and the presentation materials themselves have not been made public. Seoul Economic Daily's October 14 report likewise points out that the announcement should be understood as a plan to launch a product within the year, and that the start of mass production has not been confirmed.
Nevertheless, semiconductor-related stocks were heavily sold in the Korean market three days after the announcement. On October 13, SK hynix closed down 10.09% from the previous day at 1,443,000 won, Samsung Electronics fell 7.39% to 232,000 won, and the KOSPI dropped 5.46% to 6,035.35. At 9:47 a.m. the same day, the Korea Exchange triggered a "sell-side sidecar," temporarily halting program-trading sell orders. Samsung's shares had also fallen 4.39% on October 12, for a combined decline of about 11.5% over two trading days. However, as Reuters' market analysis reported, concerns about the profitability of AI-related investment and the interest rate outlook also contributed to that day's drop, so it cannot be said that CXMT's announcement alone was the cause.
The market's sensitivity also reflects CXMT's rapidly growing presence in the global DRAM market. According to TrendForce, CXMT's share of global DRAM revenue rose to 9.5% in the second quarter of 2026 from 7.6% in the previous quarter, putting it in fourth place. The top three are Samsung at 39.4%, SK hynix at 24.9%, and Micron at 23.3%. Counterpoint Research also estimates that CXMT's share expanded from 8% in the previous quarter to 10%. Although the figures differ somewhat by research firm, they agree that CXMT is approaching a level of about 10% of the global market.
Meanwhile, the view that has spread since the announcement, that "CXMT is two years ahead of Samsung," needs to be treated with caution. It is not a statement by Cao Kanyu himself, and Chinese media coverage of the talk, including Yicai and ITHome, contains no explanation of how many years CXMT is ahead of its rivals. The "two years ahead" comparison is one that news outlets and analysts drew between CXMT's plan to launch a product by the end of 2026 and the outlook that Samsung's 4F² products will not enter mass production until around 2028. A product announcement and the start of full-scale mass production are different stages, and this gap in timing alone cannot determine technological superiority.
17nm or 11.95nm: Why the 4F² Cell Area Comparison Flips
One important element in evaluating this announcement is the memory cell structure known as "4F²." A typical DRAM cell consists of one transistor and one capacitor, called "1T1C." Cell footprint is expressed as a multiple of F squared, where F is the minimum feature size used as the reference. The representative structure that major DRAM makers have used for many years is 6F², but with 4F², arranging the transistor vertically can theoretically reduce cell area by about 33.3% at the same F. The number of cells that fit in the same area also increases by 50% in theory.
However, adopting a 4F² structure does not necessarily make a product denser than competing products. Because actual cell area is determined by "n×F²," if F is larger, even a 4F² cell may have a larger area than a finer 6F² cell. CXMT has not disclosed the manufacturing dimensions needed for this calculation, so the comparison with competitors changes significantly depending on which dimension is assumed.
In an October 14 report, Rosenblatt Securities analyst Kevin Cassidy assumed that CXMT would build 4F² cells on a process of about 17nm, and estimated that the area would be larger than that of 6F² cells made by competitors on a process of about 12nm. His analysis, as relayed by TipRanks, points out that shrinking the cell structure alone does not create a manufacturing cost or density advantage. If 17nm and 12nm are each taken as F, CXMT's 4F² cell comes to "4×17² = 1,156nm²" and the competitor's 6F² cell to "6×12² = 864nm²." Under these conditions, CXMT's cell area is about 33.8% larger than the competitor's, and the theoretical advantage of the 4F² structure is lost to the difference in manufacturing dimensions.
However, the 17nm figure is an assumption made by Cassidy, not a manufacturing dimension that CXMT has announced it will actually use. On the other hand, in an official announcement on September 20, 2026, CXMT disclosed the start of mass production of its fifth-generation DRAM platform, "G5." According to the company, G5 uses self-aligned quadruple patterning (SAQP) to shrink the half-pitch of the active region of the memory array to 11.95nm. This is a figure CXMT published about its actual mass-production technology, and it differs in nature from the analyst's 17nm estimate.
If this 11.95nm could be used as F for a 4F² cell, the cell area would be "4×11.95² = about 571nm²." Compared with 864nm² for a competitor's 6F² cell assumed at 12nm, CXMT's cell area would this time be about 33.9% smaller. In other words, even with the same 4F² structure, assuming 17nm gives a cell about 34% larger than the competitor's, while assuming 11.95nm gives one about 34% smaller, the opposite result. This shows that not only the difference in cell structure but also the assumption about manufacturing dimensions greatly affects the density comparison.
However, these calculation results cannot be taken as evidence of CXMT's actual technological superiority. The 11.95nm announced for G5 is the half-pitch of the active region of the memory array, and is not necessarily the same dimension as the F used in 4F² cell area calculations. Moreover, the products being mass-produced on G5 and the 4F² DDR5 RDIMMs announced this time are different, and CXMT has not said that the next-generation product will use the same manufacturing dimensions as G5. Bank of America also assumes 15nm for CXMT's 4F² technology, but such estimated node values and the active-region half-pitch published by CXMT do not necessarily match in what they measure or how they are defined.
In addition, memory cell area must be distinguished from overall DRAM die area. Even if the 4F² structure reduces the cell footprint, peripheral and control circuits will not necessarily shrink by the same proportion, so the actual reduction in die area may be smaller than the reduction in cell area. Samsung, SK hynix, and Micron are also developing next-generation 10nm-class DRAM processes, and as competitors' scaling advances, the relative benefit CXMT gains from the 4F² structure will also change. What can be confirmed at this point is only that the computed advantage reverses depending on the assumed manufacturing dimensions, not an actual difference in density or manufacturing cost.
Samsung Has Also Demonstrated 4F²: What the Year-End Launch Will Show
In evaluating CXMT's technological progress, it is necessary to consider that competitors are pursuing research in the same direction. On October 13, Mizuho Securities analyst Jordan Klein listed seven reasons why CXMT's announcement does not pose an immediate major threat to companies such as Micron and SanDisk. According to the analysis reported by Investing.com, Klein pointed out that Samsung and SK hynix are also developing 4F² technology, and that this is not a breakthrough unique to CXMT but a shift to next-generation technology being pursued across the DRAM industry. He also noted that the target this time is conventional server DRAM rather than HBM, and that product specifications, yield, customer qualification, and commercial-scale shipment capability have not been presented. The view is that merely announcing a product launch plan within the year does not prove the maturity of the manufacturing technology or its cost competitiveness.
Indeed, Samsung researchers presented a prototype 16Gb SDRAM chip at the International Solid-State Circuits Conference, ISSCC 2026, in February 2026, combining 4F² cells using vertical channel transistors with a Cell-on-Peripheral (COP) structure. According to the conference paper, read and write operation was confirmed on a 10nm-class DRAM process using wafer-to-wafer hybrid copper bonding, and the number of dies per wafer increased by more than 20% under the same design rules. This shows that the technology combining 4F² and hybrid bonding has already reached the demonstration stage at Samsung as well. However, confirming that a prototype chip works at an academic conference is a different matter from being able to supply mass-produced products reliably.
Some reports say that products using Samsung's 4F² technology are not expected to reach the market before 2028. CXMT, meanwhile, plans to launch a product by the end of 2026 but has not disclosed specific specifications or production scale, so it is difficult to compare the two companies' development stages on the same basis. Jing Zhewei of Morningstar also assesses that if CXMT can put 4F² technology into practical use quickly, its competitiveness would improve significantly, but points out that it takes considerable time to go from a technology announcement to full-scale commercialization. What matters is not announcing 4F² first, but securing sufficient yield and reliability and being able to mass-produce at a competitive cost.
CXMT's technology development is also tied to US export controls on semiconductor manufacturing equipment. The rules announced by the US Commerce Department's Bureau of Industry and Security (BIS) on October 7, 2022 introduced measures requiring licenses to export certain equipment and technology to facilities in China that produce DRAM at 18nm half-pitch or below. These are not regulations targeting CXMT as a company but are based on the capabilities and uses of manufacturing facilities. The technical criteria defining the DRAM scope of the controls have since been revised, so current regulations cannot be explained by the 2022 condition of 18nm alone.
Meanwhile, according to Reuters' June 17, 2026 report, CXMT had been considered for addition to the Commerce Department's Entity List and had been approved in an interagency review, but the listing was put on hold in consideration of its possible effect on US-China trade negotiations and other factors. Entity List designation and the export controls applied to advanced semiconductor manufacturing facilities in China are different mechanisms, and not being on the list does not mean that all exports of manufacturing equipment to CXMT are freely permitted. How these regulatory lines are drawn is also important for Japanese semiconductor equipment makers.
When the US Commerce Department added about 140 Chinese companies to the Entity List in December 2024, CXMT was excluded from the targets. According to the South China Morning Post's report at the time, the background was opposition from Japan, with consideration given to the impact on Tokyo Electron, which supplies manufacturing equipment to CXMT. However, this is a report based on interviews with people familiar with the matter, and the US government has not officially explained the reason for the exclusion. CXMT is also designated on the US Department of Defense's list of Chinese military companies, but this is legally different in nature from the Commerce Department's Entity List. Developments in Chinese manufacturers' technology and US export controls bear directly on how far Japanese companies can sell manufacturing equipment in the Chinese market.
The focus going forward is whether CXMT will disclose specific manufacturing dimensions and product specifications for the 4F² DDR5 RDIMMs it plans to launch by the end of 2026. If the reference dimension of the 4F² cell is around 17nm, a simple area calculation against a roughly 12nm 6F² cell could be unfavorable. If a finer dimension has been achieved, the density gain from the 4F² structure would be larger. However, because the 11.95nm active-region half-pitch announced for G5 cannot simply be treated as the F of the 4F² cell, judging the actual advantage requires cell-area information that can be compared on the same definition.
Furthermore, a small cell area alone is not enough to fully assess competitiveness as server DDR5. In addition to transfer speed, capacity, power consumption, reliability, and manufacturing yield, qualification status on customers' server platforms is also important. Even if CXMT announces a product by year-end, that alone does not mean mass production or large-scale customer shipments have been achieved. A product announcement, customer evaluation, and stable mass production are each different stages.
While the sharp stock decline reflected wariness about CXMT's technological catch-up, the key information needed to judge its actual competitiveness has still not been sufficiently disclosed. The theoretical density gain from the 4F² structure is clear, but whether it can be translated into an advantage in manufacturing cost or product performance will depend on the maturity of mass-production technology going forward. Toward the end of 2026, the focus will be on how much CXMT reveals about its manufacturing process, product specifications, yield, customer qualification, and shipment status. Once that information is in hand, it will be possible to assess more accurately whether this announcement is an imminent threat to the leading DRAM makers in Korea and the United States, or one step in technology development for the future.