China's DRAM manufacturer CXMT is producing small quantities of HBM3E, The Information reported on August 31. According to the report, Alibaba-owned T-Head and Chinese AI chip designer Cambricon are testing CXMT-made HBM3E in combination with their own processors. The U.S. Commerce Department's Bureau of Industry and Security (BIS) added HBM to its export control list on December 2, 2024. For Chinese-made AI chips, securing a memory supply source is as pressing an issue as raw performance. If this report is accurate, domestically produced HBM has moved from a roadmap ambition to a stage where actual implementation is being evaluated.
That said, CXMT has not announced small-batch production of HBM3E, and neither the production scale nor the number of stacked layers has been disclosed. No figures have been released for capacity, bandwidth, power consumption, or yield, and the fact that testing is underway cannot be taken as confirmation of adoption. What remains before this reaches an actual product? That is what deserves scrutiny.
Small-batch production marks the entry point for implementation testing
The Information reported, citing two people familiar with the matter, that CXMT is producing HBM3E in small quantities. According to the report, T-Head and Cambricon are combining CXMT-made HBM3E with their own processors as part of adoption testing. When contacted by Reuters, CXMT, T-Head, and Cambricon all declined to comment.
HBM (High Bandwidth Memory) stacks multiple DRAM dies vertically to supply wide memory bandwidth close to AI accelerators. Because it reduces the time compute units spend waiting for data, memory itself becomes an implementation constraint for GPUs and AI ASICs. This means HBM doesn't become a finished product the moment DRAM dies are manufactured. It must go through stacking, interconnection, thermal design, and packaging, then pass reliability and performance testing in combination with a customer's processor.
The substance of the reported shift from small-batch production to adoption testing is that a prospective customer has entered that final process stage. There has been no announcement that the testing has been passed. According to The Information, if testing goes smoothly, T-Head and Cambricon plan to use the memory in products starting in 2027. A 2027 deployment is a conditional plan, and it is not yet at the stage of being treated as the start of mass production or commercial shipment.
From the AI accelerator side, adoption testing is also a verification process that precedes adding memory to a procurement list. Even if HBM's capacity and bandwidth meet design requirements, if problems emerge at the interconnects under heat or extended operation, the product cannot move forward. Since the volume of small-batch production has not been disclosed, the existence of a supply agreement has not yet been demonstrated. What has moved forward this time is the possibility that customers have begun this verification process.
HBM3E remains the mainstream choice for 2026 even as a prior generation
Samsung announced the start of HBM4 mass production and commercial shipments to customers on February 12, 2026. HBM4 is the next generation after HBM3E. Samsung has disclosed figures for HBM4 such as 11.7Gbps per pin and up to 3.3TB/s per stack, but CXMT has not published corresponding specifications for HBM3E. There is no basis for directly comparing the performance or yield of the two companies.
Even so, it would be premature to dismiss HBM3E as an outdated generation. In its 2026 market outlook, SK hynix cited multiple market forecasts suggesting that HBM3E will account for roughly two-thirds of HBM shipments that year, with HBM4's share gradually rising. In other words, even as the leading edge shifts to HBM4, HBM3E supply and evaluation as memory for AI accelerators will remain mainstream in 2026.
Here, generation names and commercial value need to be considered separately. For Chinese AI accelerators, the ability to evaluate domestic supply tailored to customer designs—in addition to procuring overseas-made HBM—becomes a factor in decision-making. That said, being one generation behind alone does not allow CXMT's product to be placed on equal footing with competing products in terms of performance or reliability; such judgments require test data.
Generation names alone do not determine commercial viability. While Samsung has announced commercial shipments, CXMT has not disclosed HBM3E specifications. What readers should verify is not the single claim that "HBM3E has been made," but rather what configuration that HBM takes and what conditions it has passed in implementation testing.
The gap in HBM within official documents
CXMT's public materials do not yet officially corroborate this report. HBM product names do not appear on CXMT's current product page, news listings, or in its May 2026 prospectus. The products listed on the product page are DDR5, LPDDR5/5X, DDR4, and LPDDR4X, and no HBM product announcement could be confirmed in the news listings either.
The prospectus, dated May 27, 2026, laid out the intended use of funds raised, totaling 29.5 billion yuan (29.5 billion RMB). The breakdown includes 7.5 billion yuan (7.5 billion RMB) for technical upgrades to mass production lines, 13 billion yuan (13 billion RMB) for advancing DRAM technology, and 9 billion yuan (9 billion RMB) for advanced DRAM research and development. No HBM-specific business is explicitly stated.
However, the absence of the HBM name in public materials does not negate the possibility of undisclosed R&D or small-batch production. It remains possible that HBM-related investment is included under the broader DRAM business name. What can be confirmed at this point is simply that CXMT's official specifications and formal announcements have not yet followed the small-batch production and adoption testing reported by independent sources.
Three conditions that will determine 2027 deployment
The first condition is customer qualification. The adoption testing by T-Head and Cambricon is the entry point for evaluating HBM in combination with their own processors. Moving toward product deployment requires passing reliability and performance testing in that combination. A report that testing is underway cannot be translated into a conclusion that adoption has been finalized.
The second is yield and supply volume. At the small-batch production stage, it remains unknown how stably CXMT can produce HBM of the required quality, or whether it can supply the volume needed to meet customer demand. Without disclosure of the number of stacked layers, capacity, bandwidth, and shipping price, accelerator designers cannot firm up their procurement outlook. There are many figures CXMT still needs to disclose.
The third is advanced packaging. HBM is not used as standalone memory; it is stacked and connected in close proximity to AI accelerators. On December 2, 2024, BIS added U.S.-origin HBM and foreign-made HBM subject to the EAR under the Foreign Direct Product Rule for advanced computing to its new export controls. Since certain HBM products are subject to exemptions, this regulation does not amount to a total ban on HBM exports to China. Even so, establishing domestic supply could remove one supply constraint in assembling Chinese-made AI accelerators.
However, even if HBM becomes domestically available, constraints remain around AI chip computing performance, software, and advanced packaging. Whether CXMT discloses official specifications, whether customers announce qualification, and whether the necessary supply volume can be sustained—only once all three conditions are met can the 2027 deployment plan be verified as an actual product.