Pandaily has reported that Chinese DRAM maker ChangXin Memory Technologies (CXMT) has designed an LPDDR6 chip operating at 12.8Gbps and is nearing completion of development verification. The product is said to be built around a 16Gb die and a 16GB PoP package. The 12.8Gbps figure is roughly 20% higher than the fastest LPDDR5X CXMT announced as a customer sample in 2025. Meanwhile, CXMT has not yet disclosed a product launch or mass production schedule for LPDDR6. Whether this effort succeeds will depend on whether the development-stage product can be handed off to customer evaluation and transitioned into stable production.
12.8Gbps Means "Nearing Completion," Not "Completed"
According to Pandaily, CXMT's first LPDDR6 has a design rate of 12,800Mbps and a base rate of 10,667Mbps, and adopts a 16Gb die. The outlet states that development verification is in its final stage, after which the product will proceed to certification in small lots before moving to full-scale mass production. In other words, the reported status is not the "completion" of development verification. Nor is it the start of mass production.
The testing cited reportedly covers everything from system compatibility to performance, power consumption, and mechanical reliability. However, the test conditions and measurement results have not been disclosed. The manufacturing process, yield, the systems evaluated, and customer names also remain unknown. The 12.8Gbps figure should be treated as a design target for the product, and must be distinguished from an effective speed confirmed in a customer device.
The most recent official disclosure also places the product at the research-and-development stage. A prospectus dated May 27, 2026 listed LPDDR6 under "preliminary research and other" as of December 31, 2025. It's possible that development verification has advanced since then, but until CXMT itself issues an update, the timing of commercialization cannot be confirmed.
Reading "16Gb" and "16GB" Separately
The report places similar-looking figures side by side: a "16Gb die" and a "16GB package." Lowercase b denotes bits, while uppercase B denotes bytes. A single 16Gb die equals 2GB, while a 16GB package equals 128Gb. If the package were built entirely from the same 16Gb dies, that would work out to eight dies in capacity terms—but the actual stack count and redundant area have not been disclosed.
The 1,295-ball PoP (Package on Package) figure likewise does not directly represent capacity or speed. PoP is a mounting method that stacks the memory package on top of the processor package, and the ball count relates to the terminal configuration connecting the two packages. Since the report contains no conditions or results for package-level verification, the 1,295 terminal count alone cannot be used to judge small-lot certification or mass-producibility.
The 12.8Gbps figure is about 20% higher per pin than CXMT's 10.667Gbps LPDDR5X. But LPDDR6's changes can't be measured by transfer rate alone. JEDEC's JESD209-6 divides a single die into two subchannels, each assigned 12 data signals. It dynamically switches between 32-byte and 64-byte access, allowing only one subchannel to be used when bandwidth isn't needed. DVFSL, which adjusts voltage and frequency to match load, has also been incorporated into the standard.
This design aims to secure bandwidth during moments of heavy data movement in AI processing while reducing power consumption during standby or light workloads. Cadence has already taped out LPDDR6/5X interface IP targeting 14.4Gbps. Thus, while 12.8Gbps is an ambitious initial figure, it does not represent an upper limit for the LPDDR6 generation.
Reliability and security features have also advanced a generation. JESD209-6 specifies PRAC, which counts how many times the same row is opened repeatedly within a short period, along with in-die ECC. In addition to link protection, it also supports scrubbing—scanning memory to remove accumulated errors. As mobile DRAM expands into automotive and AI systems, the ability to detect and contain transfer errors increasingly matters for product certification. The CXMT report contains no information yet on the implementation status or verification results for these features.
Customer Evaluation and Yield Come Before Mass Production
Looking at CXMT's own LPDDR5X roadmap makes clear the gap between development-stage products and mass-produced ones. The company moved its 8,533Mbps and 9,600Mbps products into mass production in May 2025, while its 10,667Mbps product remained at the customer-sample stage as of its October 2025 announcement. Even now, the official product page lists only up to LPDDR5/5X.
Laying out the progression over the past roughly three years by stage shows that speed increases and productization have not moved in lockstep.
| Announcement Date | Product | Speed | Status |
|---|---|---|---|
| November 2023 | LPDDR5 | 6,400Mbps | CXMT product announcement |
| May 2025 | LPDDR5X | 8,533Mbps, 9,600Mbps | Mass production started |
| October 2025 | LPDDR5X | 10,667Mbps | Customer sample |
| Current report | LPDDR6 | Design 12,800Mbps | Nearing completion of development verification |
The design target doubled from 6,400Mbps to 12,800Mbps. However, only the final row of the table comes from a media report rather than an official CXMT announcement, and thus carries a different level of certainty than the preceding three rows. Furthermore, it has not been disclosed whether the 10,667Mbps LPDDR5X has moved from customer sample to mass production. The faster the product, the more important it becomes to verify completed evaluation and stable supply separately.
In the same official announcement, CXMT clearly distinguished between the 8,533Mbps and 9,600Mbps products, labeled "mass production," and the 10,667Mbps product, labeled "customer sample." This distinction itself shows that sample provision and the start of mass production are separate states. The current LPDDR6 report contains neither designation. Even if the 12.8Gbps development product is functioning, whether shipment volumes can be steadily scaled up remains an open question.
CXMT invested RMB 9.5932546 billion in R&D in fiscal year 2025, equivalent to 15.52% of revenue. However, this is a company-wide R&D figure, not an amount spent specifically on LPDDR6. While the scale of funding indicates continued capacity for development, it does not substitute for proof of product-specific yield or completed certification.
What Comparison with Other Leading Players Reveals as Next Checkpoints
Different companies have disclosed different milestones for LPDDR6. Placing them side by side makes clear what information is still missing for CXMT.
| Manufacturer | Disclosed Stage | Specification/Timing |
|---|---|---|
| Samsung | Described product specifications and early verification with SoC companies | Up to 10.7Gbps, up to 16GB. Mass production start date undisclosed |
| SK hynix | Completed development verification of 1c LPDDR6 | 16Gb, base speed over 10.7Gbps. Plans mass production readiness in H1 2026, supply start in H2 |
| Micron | Sampling to major OEMs and others | 1γ-based 16Gb product. Mass production start date undisclosed |
| CXMT | Reportedly nearing completion of development verification (per Pandaily) | 16Gb, design 12.8Gbps. Official sample timing and mass production schedule undisclosed |
This comparison cannot be used to determine whether CXMT is ahead of or behind its rivals. Each company has disclosed different scopes of information, and design speeds have not been measured under the same test conditions. What is clear is the difference in how progress has been confirmed: SK hynix and Micron have each disclosed their mass-production-readiness and customer-sampling stages under their own names, whereas progress on CXMT's LPDDR6 can only be confirmed through media reports.
The announcement to watch for next is not a repetition of the 12.8Gbps figure, but rather CXMT's own announcement of customer sampling and a product datasheet. If that is followed by a mass production start date, adopting devices, and stable supply across multiple lots, then it will be possible to judge that this development-stage figure has translated into real-world supply capability.