On July 13, 2026, Shanghai-based semiconductor startup 东方算芯 (DFSX) unveiled its AI accelerator "DF1000." Rather than adopting the common configuration of placing external HBM (High Bandwidth Memory) alongside logic, it directly stacks DRAM and logic at the wafer level. Claiming 520TFLOPS of BF16 compute performance and 6.4TB/s of memory bandwidth on a 14nm process, the design aims to sidestep the constraints of advanced process nodes and imported HBM through both packaging and computing architecture.
The company also unveiled a technology it calls "Infinity Chiplet 3.5D+" at the same event. However, the 3D near-memory computing productized in DF1000 and the 3.5D+ concept for expanding to multiple compute chiplets are not at the same stage. While the announced bandwidth figures are high, disclosure of basic specifications, manufacturability, and real-application performance needed for product evaluation remains insufficient.
Reading 6.4TB/s and 900GB/s: An H200 Comparison
DF1000's published specifications show 14nm process, 520TFLOPS in BF16, and 6.4TB/s memory bandwidth. Card-to-card scale-up bandwidth is 900GB/s. 东方算芯 describes DF1000 as a software-defined near-memory 3D chip, positioned as an OAM 2.0-compliant accelerator card supporting training and inference for large-scale models.
For comparison, NVIDIA's H200 SXM connects 141GB of HBM3e at 4.8TB/s, with NVLink bandwidth of 900GB/s and a maximum TDP of 700W. DF1000's stated memory bandwidth is 33.3% higher than the H200's, while scale-up bandwidth matches exactly. At minimum, these specifications demonstrate that a 14nm process does not necessarily mean slower data supply.
| Item | 东方算芯 "DF1000" | NVIDIA H200 SXM |
|---|---|---|
| BF16 Compute Performance | 520TFLOPS | 1,979TFLOPS (with sparsity) |
| Memory Bandwidth | 6.4TB/s | 4.8TB/s |
| Scale-up Bandwidth | 900GB/s | 900GB/s |
| Memory Capacity | Undisclosed | 141GB |
| Maximum TDP | Undisclosed | 700W |
This table alone cannot determine overall performance superiority. While NVIDIA's BF16 figure explicitly notes the sparsity conditions used, DF1000's 520TFLOPS figure lacks the same comparative context. Furthermore, the in-house benchmark results 东方算芯 presented for Llama 3 70B and other models lack batch size and input/output length specifications. Precision and concurrent execution counts are also unclear, and neither power consumption nor the comparison system used has been disclosed. 6.4TB/s is an impressive number, but how much data it can hold, at what power draw, and how many tokens it can process for actual models must be measured separately.
Moving HBM Aside and Placing DRAM Above Logic
HBM is itself a 3D memory that stacks multiple DRAM dies using TSV (Through-Silicon Via) technology. In current AI GPUs, the mainstream configuration places this HBM stack beside the logic, connecting the two via a silicon interposer with wide I/O—a 2.5D structure. What DF1000 changes is not whether 3D stacking occurs, but where memory and compute units are physically located.
According to 东方算芯's official explanation, the DRAM layer and logic layer are vertically connected via bumpless hybrid bonding. Connection pitch shrinks from tens of micrometers in conventional designs down to sub-micrometer scale, enabling shorter, denser wiring that increases bandwidth density. The company claims over 5x the bandwidth compared to equivalent-capacity HBM, but has not disclosed DRAM capacity, the number of stacked layers, or which HBM generation was used for comparison. Rather than relying on this multiplier claim, it is safer to treat the 6.4TB/s figure for the standalone product as the starting point for evaluation.
On the compute side, this is supported by a "software-defined chip" that reconfigures hardware resources and connection pathways according to use case. This reconfigurable architecture, long advocated by 东方算芯 Chairman and CEO Wei Shaojun (魏少軍) at Tsinghua University, uses asynchronous dataflow organized around units called Tensor Tiles, overlapping computation and data movement in execution. Rather than increasing transistor count through process miniaturization, the aim is to reduce idle time for existing resources, extracting greater effective performance from the 14nm process.
3D Near-Memory Computing and Infinity Chiplet 3.5D+ Are at Different Stages
What DF1000 has brought to full product pages is a single chip with vertically stacked DRAM and logic, plus an OAM 2.0 card. Infinity Chiplet 3.5D+ is 东方算芯's proprietary name for extending this near-memory computing stack to multiple compute chiplets. It should not be treated as an industry-standard packaging specification name.
The key insight behind this concept is freeing up two resources that external HBM previously occupied. The first is package area—the same footprint can now accommodate more compute chiplets. The second is logic-side I/O, where the area previously dedicated to HBM connections can be reallocated to inter-chiplet links. The idea is that 3D DRAM sitting directly above the compute unit handles local data supply, while lateral connections are concentrated on scaling up across multiple chips.
However, what was presented at the launch event were structural advantages only—the die count, connection method, and package dimensions for Infinity Chiplet 3.5D+ remain undisclosed. Manufacturing timeline and adopting products are also unknown. There is no guarantee that DF1000's 6.4TB/s can be linearly extended across multiple chiplets as-is. The current product's 3D DRAM and the future multi-chiplet concept need to be read as separate matters.
The Value of a Fully Domestic Supply Chain Depends on Mass Production, Not Just Regulation
东方算芯's reasons for eliminating external HBM extend beyond design efficiency to procurement concerns. On December 2, 2024, the U.S. Bureau of Industry and Security (BIS) added HBM as a new subject of export controls, as part of measures restricting China's advanced semiconductor capabilities. The regulation covers not only U.S.-origin products but also certain foreign-made HBM subject to the Foreign Direct Product Rule for advanced computing. For companies aiming to continuously supply AI accelerators within China, the incentive to shift memory procurement domestically is clear.
Regarding DF1000, 东方算芯 states that it has structured everything from wafer fabrication to packaging/testing, servers, and clusters through a domestic Chinese supply chain. The company's official website features product pages for the DF1000 card, the 64-card "拓域 TY64" system, and servers/clusters, along with published documentation for the CAAP software stack. The launch event showcased configurations ranging from 8-card modules up to 512-card systems. This confirms an approach that extends beyond a standalone die to include deployment formats.
On the other hand, the official TY64 page describes the product as a current key R&D focus. The manufacturing foundry for DF1000, the DRAM supplier, and the company handling hybrid bonding remain undisclosed. Monthly production volume, pricing, and customer names are also unknown. Having product pages and contact channels does not itself prove stable mass-production shipping or large-scale deployment. The self-sufficiency of the supply chain can only be properly evaluated once the constituent companies and production volumes become visible.
Even at 90% Yield Per Die, Two Layers Drop to 81%: The Stacking Yield Barrier
Hybrid bonding itself is not an unknown process. According to an overview presented by Adeia at the January 2026 IEEE Hybrid Bonding Symposium, wafer-to-wafer bonded image sensors and single-layer memory-on-logic configurations have already entered mass production. However, for applications stacking numerous dies, mass-production adoption has not yet been achieved, and work remains to maintain bonding yield while controlling warpage and defects.
In an interview with Jiemian News, Wei Shaojun explained that if each die's yield is 90%, combining two layers would yield 81%. This is not an actual measured value for DF1000, but a hypothetical example illustrating how yield declines with increased stacking count. The bandwidth advantages of sub-micrometer connections cannot be separated from the proportion of good dies that can actually be extracted during mass production.
For its next-generation DF2000, 东方算芯 plans to launch a product in Q4 2026 targeting 1000TFLOPS in BF16, 15TB/s memory bandwidth, and 1600GB/s scale-up bandwidth. The DF3000 is planned to push these figures further to 2000TFLOPS, 20TB/s, and 3200GB/s by Q4 2027. Both remain planning figures at this stage.
What DF1000 demonstrates is the possibility of charting a different performance curve by redesigning data supply to compute units, even when advanced process nodes and HBM access are limited. Whether memory capacity, TDP, and stacking yield will be disclosed by Q4 2026—when DF2000 is planned to launch—remains to be seen. If model performance under consistent conditions and operational deployment with actual customers can also be confirmed, this design could be judged to have progressed from a constraint-driven workaround to a reproducible product technology.