A research team including Diraq and the Belgian semiconductor research institute imec has tuned and individually controlled all eight silicon spin qubits fabricated on a 300mm CMOS-compatible process. The results were published in Nature Communications on July 9, 2026. In 2025, a two-qubit device built on the same fabrication platform had already recorded operation fidelities exceeding 99%. This time, the team extended that platform to a row of eight qubits and measured Rabi oscillations and coherence across all of them. The challenge has shifted from "can the fab produce high-quality qubits" to "how do you read and connect a large number of qubits."
Eight Qubits Grouped into Four Pairs, All Individually Controlled
The prototype chip has eight quantum dots arranged in a straight line. The research team grouped adjacent pairs into units called double quantum dots, organizing the array into four pairs for tuning. Rather than handling all eight at once, the design creates four well-understood two-qubit units. The team states that this grouping allows tuning to be broken down into N/2 unit cells for N qubits.
Across all eight qubits, the team observed Rabi oscillations, in which microwaves periodically drive changes in the quantum state. Rabi frequencies fell within a range of 141–204.5 kHz, allowing each qubit to be addressed and operated by frequency. The Ramsey coherence time T2*, which includes the effects of external noise, reached a maximum of 41 microseconds with an average of 21 microseconds. The Hahn echo T2, which cancels out slow noise, reached a maximum of 1.31 milliseconds with an average of 0.7 milliseconds. According to the paper, these figures are comparable to foundry-fabricated devices of the same lineage and exceed comparison devices made in university research facilities.
The fabrication conditions also narrow and clarify what this result means. imec used isotopically purified silicon-28 on 300mm wafers, keeping residual silicon-29 down to 400 ppm. The gate pitch was 90nm, using a combination of optical lithography and electron-beam lithography. Measurements were performed inside a dilution refrigerator at about 20mK. While the same 300mm-diameter fabrication platform used for ordinary logic semiconductors was employed, this does not mean the chip has become a mass-producible device operating at room temperature.
Extending a Two-Qubit Unit Cell into a Long Row of Eight
In the preceding 2025 Nature paper, the team examined four two-qubit devices designed by Diraq and fabricated by imec, all of which exceeded 99% control fidelity for both single-qubit and two-qubit operations. State preparation and readout reached up to 99.9%, T2* reached up to 40.6 microseconds, and the Hahn echo T2 reached up to 1.9 milliseconds. The first achievement was showing that an industrial process could reproduce precision close to that of laboratory-made devices.
In the current eight-qubit work, the peak coherence times were not improved upon. The value lies instead in quadrupling the number of devices using the same 300mm process while achieving individual control of all eight. As qubit count increases, gate electrode variability, interface defects, and interference with neighboring quantum dots make tuning more difficult. Nevertheless, since all eight could be operated, the prospect of transferring unit-cell performance to a long row has become somewhat more concrete.
However, using a 300mm wafer is a separate matter from demonstrating production yield. The paper's detailed measurements were conducted on a single eight-qubit device, and it does not show what fraction of the many chips on a wafer would operate with the same performance. The 2025 study confirmed reproducibility across four two-qubit devices selected from the same wafer, but the yield distribution when scaling to eight qubits remains a verification item for the future.
Reading the Central Four Qubits from Two Sensors at the Ends
In a linear array, how the interior of the row is read affects wiring density. This chip placed a single-electron transistor (SET) at each end of the row. The two pairs at the ends are read directly by the SETs, while the charge transfer corresponding to the quantum state of the central two pairs is cascaded outward. This is a "cascade readout" that carries distant changes to the sensors at the ends.
This allowed the central four qubits to also be measured with a high signal-to-noise ratio. The two pairs at the left and right ends are acquired simultaneously, and the central two pairs are acquired simultaneously in a separate stage. Although this is not a method for reading all eight at once, it allowed the entire row to be measured in two stages without adding a sensor and wiring for each individual qubit. As the number of devices increases, the wiring brought into the refrigerator becomes a source of heat influx. A design that suppresses the growth in sensor count is effective for balancing qubit density with cooling load.
The research team believes this method can be extended to even longer one-dimensional rows. However, in more complex chips, sequentially loading electrons into every quantum dot from the end would take considerable time for initialization. The paper proposed an alternative approach: preparing electrons at the ends and shuttling them inward. Beyond readout, control that transports electrons and quantum information without destroying them will be needed.
One Two-Qubit Gate Pair Demonstrated; Full Connectivity Not Yet Shown
Even with individual control of all eight qubits achieved, quantum computation requires operations that make adjacent qubits interact. The research team controlled the exchange interaction for one pair at the end, P1–P2, and examined the phase of a controlled-Z (CZ) gate over up to 38 repetitions. Since phase consistency was maintained, the authors suggested that the surrounding charge noise may be low.
However, the paper does not report the fidelity of this CZ gate. For the remaining three pairs, the exchange interaction could not be smoothly turned on even as voltage was increased. This was due to unintended quantum dots forming in unexpected locations or electrons shifting to different positions. For P7–P8, the interaction strengthened abruptly, which was unsuitable for precise gate control.
The authors explicitly state that this result does not demonstrate the scalability of two-qubit gate tuning. To confirm whether the concept of tuning eight qubits as four pairs is truly scalable, stable entangling gates must be operated in each pair. This chip has reached the stage of "keeping eight qubits in the same row and handling them individually," but not the stage of "freely linking eight qubits together as a computational circuit."
Beyond the 90nm Pitch: Two-Dimensional Connectivity and Yield
The direct improvement for stabilizing exchange interactions is to shrink the gates and tighten the pitch between quantum dots. The 90nm pitch is a design point along the path of extending the fabrication technology, and the paper explains that further miniaturization would confine electrons more strongly, making it easier to tune the coupling between adjacent qubits. However, uniformity and yield across the entire wafer must be maintained even as miniaturization proceeds.
The shape of connectivity will also change. A one-dimensional row is convenient for studying synchronized control and statistics, but large-scale error correction requires a two-dimensional structure with more neighboring relationships. imec has proposed bilinear and trilinear structures that fold a two-dimensional lattice into two or three rows, along with a scheme for shuttling quantum information within a row. The eight-qubit linear array serves as an entry point for testing these wiring, readout, and shuttling technologies.
On the manufacturing side, the European semiconductor quantum pilot line "SPINS," led by imec, launched in April 2026. It involves 25 organizations with a project scale of 50 million euros, and aims to provide research-oriented multi-project wafers and initial design kits — an effort to move from a single company's prototyping toward a fabrication platform usable by multiple designers.
Diraq's roadmap is also under review by the U.S. Defense Advanced Research Projects Agency (DARPA) as part of its Quantum Benchmarking Initiative. The company advanced to Stage B in November 2025, where over the course of a year its R&D plan, risk mitigation measures, and required prototypes will be evaluated. QBI assesses whether "utility-scale" computing — where computational value exceeds cost — can be reached by 2033. The next evidence needed toward that goal is not simply an increase in qubit count. Once gate fidelity across all neighboring pairs, two-dimensional connectivity, and wafer-level yield are all in place, the 300mm process will connect its manufacturing advantages to computational scalability.