Dongfang Suanxin, a semiconductor startup based in Shanghai, China, unveiled its first AI accelerator, the "DF1000," on July 13. Despite using a 14nm process, it claims 520 TFLOPS in BF16 and memory bandwidth of 6.4TB/s. Rather than increasing transistor count through miniaturization, the company chose a design that vertically stacks logic circuits and DRAM, reconfiguring compute resources according to workload. As US export controls make it harder to procure leading-edge manufacturing equipment and high-bandwidth memory, this reveals where Chinese AI chip development is trying to carve out a detour.
However, it is premature to call the DF1000 a substitute for the NVIDIA H200. What has been disclosed centers on peak compute performance and bandwidth. Memory capacity and power consumption remain unknown, and neither mass-production yield nor actual training times using large-scale models have been shown. What Dongfang Suanxin has moved is not the outcome of the competition itself, but the very yardstick used to judge it.
Layering Stacking and Reconfigurability onto 14nm
The DF1000's design rests on two pillars: "software-defined computing" and "3D DRAM near-memory computing." According to Dongfang Suanxin, the compute side supports multiple precisions from FP32 to FP4, dynamically reconfiguring data paths to match the model. It adopts an asynchronous dataflow built around Tensor Tiles as the basic unit, overlapping computation with data transfer. This design philosophy aims to combine the versatility of a GPU with the efficiency of an ASIC (application-specific integrated circuit).
On the memory side, the logic circuit layer and the DRAM layer are directly stacked using hybrid bonding. Because this eliminates the need for tiny solder bumps and instead bonds copper wiring and insulating film directly, Dongfang Suanxin explains that the spacing between interconnects across layers can be shrunk from the tens-of-micrometer scale of conventional approaches down to the sub-micrometer scale. This shortens wiring and allows more interconnects to be added. The 6.4TB/s memory bandwidth figure is the first number this vertical connection produces.
In large-scale model training, even fast compute units incur wait time if weights and intermediate data cannot be supplied quickly enough. Inference, especially token-by-token generation, also tends to be bandwidth-bound. The DF1000 attempts to compensate for the compute-density disadvantage of 14nm by shortening the distance and time required to move data.
How to Read the 6.4TB/s and 520 TFLOPS Figures
Among the disclosed figures, memory bandwidth is where the DF1000 appears strongest. Its 6.4TB/s exceeds the 4.8TB/s that NVIDIA publishes for the H200 SXM. The chip-to-chip scale-up bandwidth is 900GB/s, matching the publicly stated figure for the H200's NVLink.
| Metric | Dongfang Suanxin DF1000 | NVIDIA H200 SXM | Notes for Comparison |
|---|---|---|---|
| Manufacturing process | 14nm | Not disclosed | DF1000 promotes use of a mature process |
| BF16 peak performance | 520 TFLOPS | 1,979 TFLOPS | H200 figure assumes use of sparsity; DF1000's conditions are undisclosed |
| Memory bandwidth | 6.4TB/s | 4.8TB/s | Capacity and effective bandwidth also need to be considered |
| Scale-up bandwidth | 900GB/s | 900GB/s | Communication method and collective-communication efficiency require separate verification |
| Memory capacity | Not disclosed | 141GB | Affects the scale of trainable models and parallelization |
| Max power consumption | Not disclosed | 700W | Cannot compare performance-per-watt or operating costs |
The BF16 figures should not be taken as a direct ratio. The H200's 1,979 TFLOPS figure relies on sparsity to make computation sparse, and it is not disclosed whether the DF1000's 520 TFLOPS figure includes the same condition. Peak values also say nothing about how well compilers and compute libraries can actually fill the compute units. Dongfang Suanxin itself states that surpassing the H200 is a goal for its next-generation DF2000, not the DF1000.
The bandwidth advantage also comes with caveats. The DF1000 has not disclosed its memory capacity, making it impossible to judge how many cards a model would need to be split across. During training, gradient synchronization occurs every time computation crosses card boundaries. Even with a physical bandwidth of 900GB/s, if the collective-communication library or network configuration is weak, performance gains from adding more cards will taper off.
The Constraint Shifts to Bonding Yield and Software
The DF1000 is not a product that nullifies export controls. In December 2024, the US Bureau of Industry and Security (BIS) added restrictions covering 24 types of equipment used in advanced semiconductor manufacturing, three types of design and manufacturing software, and high-bandwidth memory (HBM). Meanwhile, as of January 2026, exports of the H200 and AMD's MI325X to China have shifted to a case-by-case review process for customers who meet security requirements. The controls are strict, but they are not a system that uniformly blocks all advanced AI chips.
Dongfang Suanxin's response is to align its design with parts that can be made using 14nm and domestic supply chains, spreading out the procurement risk that had been concentrated on HBM and leading-edge nodes. If this holds, the company's product plans would become less vulnerable to shifts in export licensing. That said, while the company touts a "domestic supply chain," it has not disclosed its manufacturing foundry, the type of DRAM used, or the supplier of its bonding equipment. How much of the process is truly completed domestically cannot be verified.
Moreover, hybrid bonding does not eliminate manufacturing difficulty. Bonding surfaces require high flatness and cleanliness, and even minor particles or misalignment can cause connection failures. Attempting to screen for known-good dies before stacking risks damaging the delicate bonding surfaces with probes, which can affect subsequent processing steps. According to industry sources cited by SemiEngineering, one reason current HBM4 has held off on transitioning to hybrid bonding and continues to use micro-bumps is exactly this yield and inspection challenge. CEO Wei Shaojun himself has acknowledged that yield can decline as the number of stacked silicon layers increases.
Another major hurdle is software. Dongfang Suanxin says it has optimized for models such as DeepSeek, Qwen, and GLM, and that its proprietary CAAP software suite supports major AI frameworks and operator development. However, the scope of supported operators, the stability of distributed training, and the effort required to port existing CUDA code remain unclear. Extracting peak performance in real applications requires refining compilers and kernels, as well as maintaining long-term stability in communication and fault monitoring.
Gauging Practicality Through Shanghai Deployment and a 64-Card Cluster
Rather than emphasizing the chip alone, Dongfang Suanxin is foregrounding a deployable system as a whole. The DF1000 card complies with the OCP Accelerator Module (OAM) 2.0 standard, making it easier to integrate into AI servers built by domestic OEMs. OAM is a specification that defines common requirements for accelerator dimensions, power, cooling and management, and high-speed interconnects, reducing the burden of redesigning servers for each proprietary card.
Surrounding products include the "TY64," a 64-card supernode using standard Ethernet, the "QY100," a high-density liquid-cooled server, and the "HS512," a cluster on the order of 512 cards. This suggests an approach that views NVIDIA's strength not merely in terms of single-chip performance, but as encompassing the networking and operational software that binds multiple cards together. OAM compliance widens the entry point for hardware adoption, but it does not guarantee CUDA compatibility.
The first proving ground will be Shanghai. On July 7, Wei Shaojun told United Daily News that starting in the second half of 2026, the company would deploy the DF1000 to companies, universities, and research institutions in Shanghai, primarily for large-scale model training in the cloud. At the July 13 announcement, the company also stated that mass-production preparations are complete and that it expects to begin shipments by year-end. Since customer names, unit counts, and utilization rates have not been disclosed, this should currently be viewed as an early-deployment plan rather than a confirmed rollout.
Practicality can be measured by the time required to train the same model to the same precision. Next, looking at the performance-scaling ratio and downtime frequency when scaling up to 64 cards would reveal the maturity of the communication and software stack. If power consumption and cooling costs are also disclosed, it will become possible to judge the economics of using a 14nm process as well.
Less Than Six Months to DF2000: Real-World Measurements Will Sort Out the Roadmap
Dongfang Suanxin's plan moves fast. According to SCMP, the company aims to double the DF1000's capability with the DF2000, targeting a performance level beyond the H200, and launch it in Q4 2026. It then plans to double performance again with the DF3000 in Q4 2027, aiming to compete with NVIDIA's B300. Because full-scale DF1000 shipments and the DF2000 launch both fall around the same year-end period, the timeline for product-generation updates and customer-side evaluation will proceed in parallel.
What will underpin this roadmap is not an increase in peak TFLOPS, but mass-production data. Will memory capacity and power consumption be disclosed by year-end, and will Shanghai deployment partners be able to demonstrate actual training times and cluster utilization rates? Furthermore, will hybrid-bonding yield reach a level that can sustain both pricing and supply volume? If all three conditions are met, the DF1000 will add a genuinely new option to China's AI computing infrastructure. If they remain unmet, the combination of 14nm and 3D stacking will stay a promising design concept rather than a proven product.