GlobalFoundries' (GF) next-generation chip manufacturing technology, FDX Fusion, is slated to begin production for early customers in 2028, with high-volume manufacturing targeted for 2030. The details came from an interview published by Tom's Hardware on November 6 with Sudipto Bose, GF's vice president of its FD-SOI business unit. The technology aims for 7nm-class digital performance while using planar transistors. The interview also revealed a logic density target of 14 million gates per mm², and that new manufacturing equipment will be needed even though EUV lithography is not. The "production start in 2028" announced officially in October did not necessarily mean the start of large-scale volume supply.
From initial production in 2028 to volume manufacturing in 2030
In its official announcement on October 9, GF said it planned to begin manufacturing FDX Fusion at its Dresden, Germany fab in 2028. In the Tom's Hardware interview, Bose explained that what is planned for 2028 is production for early customers, with high-volume manufacturing targeted for 2030. He added that the timing of the move to volume production will depend on how those early customers progress and which applications are adopted.
FDX Fusion production plans and the Dresden fab expansion
| Date announced | Target / stage | Target timing | Details |
|---|---|---|---|
| Oct. 9, 2026 | Start of FDX Fusion manufacturing | 2028 | GF's original official announcement |
| Nov. 6, 2026 | Initial-customer production of FDX Fusion | 2028 | Bose clarified the stage at manufacturing start |
| Nov. 6, 2026 | High-volume manufacturing of FDX Fusion | 2030 | Target that depends on early customers and applications |
| GF's Dresden expansion plan | Fab-wide capacity expansion under SPRINT | End of 2028 | Expands 300mm wafer capacity to more than 1 million wafers per year. Not capacity dedicated to FDX Fusion |
This explanation makes clear that the 2028 manufacturing start and the 2030 volume target refer to different production stages. 2030 is not a firm commitment for the start of volume production, and there is no basis for concluding that the manufacturing plan was delayed between October and November. The expansion of the Dresden fab's overall capacity should also be distinguished from FDX Fusion's standalone supply capacity.
GF is pursuing the Dresden expansion through "SPRINT," a €1.1 billion investment. The company plans to raise the fab's overall 300mm wafer capacity to more than 1 million wafers per year by the end of 2028. That figure, however, does not represent capacity dedicated to FDX Fusion. In addition, starting FDX Fusion technology development is conditional on approval by the German government under IPCEI AST. The fab-wide expansion, the preconditions for technology development, and the volume production schedule for an individual process each need to be assessed separately.
7nm-class performance at 14 million gates per mm²
GF has set targets for FDX Fusion of more than double the density of the first-generation FDX and 7nm-class digital performance. The figure of 14 million gates per mm² that Bose disclosed is a measure of logic density. A gate here is a unit of logic circuitry, not a single transistor, so the number cannot be treated directly as transistor density.
According to Bose, FDX Fusion's density is equivalent to the 8nm class, while it aims for 7nm-class power efficiency, such as compute performance per watt. Citing different process generations for density and performance reflects the fact that different metrics are being compared. The term "7nm-class" does not refer to a specific physical dimension of the transistor, nor does it guarantee parity with other companies' 7nm processes in every aspect of performance or specification.
Nor can total chip area be calculated simply from logic gate density. Real semiconductors include not only logic circuits but also SRAM, analog circuits, and more, each with different area and design requirements. Detailed dimensions such as pitch, which describes the spacing of transistors, are due to be published later, so this figure alone makes a rigorous density comparison with other companies' processes difficult.
GF has also set specific improvement targets against the current FDX for performance and power consumption: 30% higher performance at the same power, or 40% lower power at the same performance. Both targets include the use of dynamic body biasing, and they do not mean a 30% performance gain and a 40% power reduction are achieved simultaneously under the same operating conditions. In actual product design, the benefit depends on whether a designer holds power constant to raise processing performance, or maintains the required performance while cutting power.
How planar FD-SOI boosts performance
FD-SOI (Fully Depleted Silicon on Insulator) is a technology that builds transistors in an extremely thin silicon layer formed on top of an insulating film. According to GF's technology overview and STMicroelectronics' explanation, combining a buried oxide layer with a thin silicon layer improves the electrical control of the transistor while keeping a planar structure. This differs from FinFETs, which shape the silicon into three-dimensional fins.
One feature of FD-SOI is that the threshold voltage at which a transistor turns on can be adjusted by applying a voltage to the substrate side. This makes it possible to raise operating speed when high processing performance is needed and to suppress leakage current during standby. The technique of varying the substrate voltage according to operating conditions is called "dynamic body biasing," and it is used to flexibly balance performance and power consumption. However, it cannot maximize both speed and power savings under all operating conditions at once, and control tailored to the application is required.
FDX Fusion also involves improvements to the substrate material. According to an EE Times interview with Manfred Horstmann, head of GF's European fabs, GF is working with CEA-Leti and Soitec to develop a "strained silicon substrate," in which strain applied to the crystal structure improves carrier mobility. While keeping the basic planar transistor structure, there is room to improve performance by combining materials technology with body-bias control. These, however, describe technical mechanisms and development policy, not evidence that FDX Fusion has achieved its target performance in measurements.
In its August 2018 policy announcement, GF put development of 7nm FinFET on hold indefinitely and said it would strengthen investment in differentiated manufacturing technologies. FDX Fusion is not a resumption of the FinFET development suspended at that time; it is positioned as GF's own manufacturing technology that evolves FD-SOI.
No EUV, but new equipment and more complex processes are required
GF emphasizes that FDX Fusion aims for 7nm-class digital performance without EUV (extreme ultraviolet) lithography. By not requiring EUV exposure tools, the company aims to achieve competitive mask costs and other savings. Bose, however, explained that manufacturing FDX Fusion requires new equipment and that the process flow will be more complex than the existing 22nm FD-SOI or 12nm FinFET. In other words, not needing to install EUV tools does not mean existing equipment can be reused as is.
Horstmann supplemented the manufacturing details in the EE Times interview. According to him, FDX Fusion will use ArF immersion lithography and is expected to use about 50 photomasks in the initial phase. Even without EUV, masks for forming fine circuit patterns and new substrate materials are needed. As process complexity rises, process control and capital investment also affect cost, so the mask count of about 50 alone cannot determine the manufacturing cost difference versus other processes.
Incidentally, manufacturing 7nm-class chips without EUV is not an industry first. In its October 2019 announcement, TSMC positioned N7+ as its first EUV volume-production technology, but the preceding N7 process had already been in volume production for more than a year. The "7nm" process-generation label therefore does not necessarily imply the use of EUV.
At this point, FDX Fusion wafer pricing and the rate of reuse of existing equipment have not been disclosed. No specific figures are available either for yields at volume production or for the manufacturing cost per good chip. GF aims to hold down mask costs and other expenses by avoiding EUV, but how far that translates into lower cost per good die will have to be judged from the actual manufacturing process and production results.
For edge AI chips, functional integration and cost per good die are key
Given these technical characteristics and manufacturing costs, assessing FDX Fusion's competitiveness depends not only on simple gate density but on how much of the required product functionality can be implemented at what power and cost. In robotics, automotive, and industrial equipment, the main applications GF envisions, products need not only digital computation but also sensor signal processing and external communications. Comparing the performance of compute circuits alone cannot adequately evaluate a product's overall power consumption or manufacturing cost.
GF plans for FDX Fusion to integrate RF (radio-frequency) and analog/mixed-signal circuits and to support embedded non-volatile memory and in-memory computing. For fT/fmax, an RF performance metric, it targets up to 0.5THz. However, fT and fmax indicate a transistor's high-frequency characteristics and do not mean digital circuits will run at 0.5THz. FDX Fusion's performance should be evaluated using metrics suited to each function, including digital computing, RF, analog circuits, and memory.
The richness of design assets is another key factor affecting product development cost and schedule. GF's existing FDX platform offers more than 700 IP blocks (circuit assets that can be reused in designs). But not all of them have necessarily been ported to FDX Fusion and verified. Even if the required wireless communications circuits and memory technologies are supported, insufficient verification of the IP in use could affect product development time and cost.
The customer engagements GF cited in its October announcement are at an early development and evaluation stage and do not mean volume adoption has been decided. In the 2028 production for early customers, power efficiency on actual silicon and the maturity of functional integration will be key points of evaluation. Whether GF can carry those results into a volume production setup by 2030 and demonstrate competitiveness, including yield and cost per good die, will shape how widely the technology is adopted. FDX Fusion's value will be judged not by the "7nm-class" label, but by how efficiently and economically it can combine low-power computing with functions such as communications.