A report published October 7, based on Damnang's interviews with engineers, says SK hynix is struggling to develop hybrid bonding for next-generation HBM, while Samsung has pulled ahead by shipping samples that use the method.
HBM (high-bandwidth memory) stacks multiple DRAM chips vertically to feed large volumes of data to AI semiconductors. Changing the bonding method affects how many chips can be stacked, how tall the package is, and how well it dissipates heat.
However, the development status described in the report does not come from official announcements by either company. SK hynix has already shipped samples of HBM4E that use its existing bonding method.
Even if Samsung leads in hybrid bonding prototypes, that lead translates into a mass-production advantage only if it can bond copper with high precision and also repeat the entire process, from polishing through bonding, reliably.
What hasn't been prototyped is the new bonding method, not next-gen HBM as a whole
The information is based on an interview with a process development engineer at SK hynix's Future Technology Research Institute.
According to the introduction of Damnang's interview article, published October 6, the interview took place on September 19 and lasted about 90 minutes, Pacific time. It also states that the remarks reflect the engineer's personal views, not the company's official position.
A report quoting a post by P Equity Research that introduces the interview says SK hynix has technical problems with hybrid bonding and has not yet begun producing HBM samples with it, while Samsung has already shipped samples to customers.
That comparison, however, reached readers through a secondary report, and the full interview is behind a paywall. The HBM generation, the number of stacked layers and the customers involved cannot be confirmed. Nor can an engineer's view from September be treated as the settled state of development in October.
The key point here is that not having made progress on prototypes with the new bonding method is different from being unable to prototype next-generation HBM itself.
In its June 18 announcement, SK hynix said it had shipped samples of 12-layer HBM4E to major customers. The capacity is 48GB, and the product uses Advanced MR-MUF for bonding.
This is the method the company has refined over the years: chips are connected with tiny metal contacts, and a liquid protective material is flowed into the gaps and hardened.
SK hynix also said this HBM4E improves thermal resistance by 17% compared with the previous-generation HBM4.
Even if the new hybrid bonding technology faces challenges, work is already under way to move next-generation products into customer evaluation as an extension of existing processes. This testimony alone does not support the conclusion that SK hynix's entire HBM4E development has stalled.
Bonding copper directly requires aligning the entire process, not just the bonding surface
Hybrid bonding connects the copper on chip surfaces directly, without solder microbumps.
It also bonds the insulating films around the copper, which is why it is called "hybrid." If the space taken up by connections and the material filling between layers can be reduced, more DRAM can be stacked within a limited package height.
The distance electrical signals travel also becomes shorter, which could reduce signal loss and power consumption. Removing organic materials, which conduct heat poorly, from the bonding interface could also help with heat dissipation.
However, "pitch," the spacing between terminals arranged side by side, is a different dimension from the distance between upper and lower chips. Demonstrating a fine connection pitch does not mean that mass-production technology for multilayer HBM is complete.
Applied Materials' process explanation describes why the shape of the copper surface determines bonding quality.
Chemical mechanical polishing (CMP), which combines chemical reaction with mechanical polishing, planarizes the insulating film, and the copper pads are left recessed by a few nanometers below that surface.
The insulating films are bonded first, and heating then expands the copper so that the copper pads touch each other.
If the copper is recessed too deeply, voids remain at the bonding surface; if it protrudes too far, it can cause delamination.
Simply "polishing flat" is not enough. The height relationship between the insulating film and the copper must be kept uniform across the entire surface being bonded.
Particles generated during polishing and chip dicing, contaminants left on the surface, and edge defects also interfere with adhesion.
Surfaces prepared for bonding with plasma and similar treatments also change in character over time. Applied Materials explains that the time between surface activation and bonding, and even the clean environment used to transport wafers between processes, must therefore be controlled.
Even if a bonding tool achieves high alignment accuracy once, variation in the processes before and after it will prevent stable bonding quality.
HBM adds the difficulty of handling even thinner dies.
According to Applied Materials' August 18 explainer on HBM manufacturing, DRAM dies must be thinned to keep the overall package height while increasing the number of layers.
Thinner chips are more prone to warping under stress. As stacks grow from 12 layers to 16 or more, the risk of yield loss from misalignment and bonding defects also rises.
These are manufacturing challenges common to hybrid bonding and high-stack HBM.
It has not been disclosed which process SK hynix is actually struggling with, so it cannot be concluded that CMP or chip warping is the direct cause of the delay.
Still, it is clear that hybrid bonding is not a technology that can be solved simply by installing new bonding equipment; the entire manufacturing process, including the steps before and after, must be stabilized.
Comparing who is "ahead" requires matching bonding methods and development stages
In a March 17 announcement for GTC, Samsung introduced its hybrid copper bonding technology, HCB.
It positions the technology as supporting next-generation HBM with 16 or more layers, and says it can reduce thermal resistance by more than 20% compared with conventional thermal compression bonding (TCB).
This is technology development consistent with the report that Samsung leads in sample shipments, but the March announcement itself does not mean mass production of HBM using HCB has begun.
Samsung's HCB showcase, SK hynix's HBM4E sample shipments using MR-MUF, and imec's wafer bonding demonstration each involve a different target and a different development stage.
| Announcing party / date | Bonding target and method | Stage announced | Conditions for reading the numbers |
|---|---|---|---|
| Samsung, March 17, 2026 | HCB for next-gen HBM with 16+ layers | Bonding technology introduced at GTC | The 20%+ thermal resistance reduction is versus TCB. Not an announcement of mass production or customer qualification |
| SK hynix, June 18, 2026 | 12-layer, 48GB HBM4E, Advanced MR-MUF | Samples shipped to major customers | The 17% thermal resistance improvement is versus the previous-generation HBM4. Not a hybrid-bonded product |
| imec and EV Group, May 28, 2026 | Test structures bonding wafer to wafer | 200nm pitch of copper pads demonstrated | Post-bonding overlay vector under 40nm for all dies on 300mm wafers. Not performance in HBM mass production |
The table organizes Samsung's announcement, SK hynix's sample shipment announcement and imec's research announcement by target and stage reached.
It lists only officially confirmed announcements; the testimony about Samsung's sample shipments is not included in the technology showcase column.
In particular, one cannot judge Samsung to be superior by comparing the thermal resistance figures of "more than 20%" and "17%."
The former compares a bonding method with TCB, while the latter compares a product with the previous-generation HBM4. They were not evaluated with the same stack configuration or measurement conditions.
Thermal resistance indicates how difficult it is for generated heat to escape. A reduction in thermal resistance should also be distinguished from a reduction in the chip's own power consumption.
imec's result is also some distance from HBM mass production.
The May demonstration bonded two wafers with formed wiring together in a single batch.
In an explanation by Professor Seunghwan Joo of Inha University, published on the SK hynix Newsroom, he describes the difference between wafer-to-wafer methods, which bond wafers together at once, and die-to-wafer methods, which place individual chips on a wafer.
Wafer-to-wafer bonding can process many chips at once, but defective dies are bonded along with good ones, which tends to affect yield.
Die-to-wafer bonding allows only good dies that passed inspection to be selected and stacked, but placing them one by one makes throughput a challenge.
Professor Joo explains that for HBM, die-to-wafer is moving toward commercialization.
The high alignment accuracy achieved when bonding wafers in bulk and the mass productivity of HBM, which stacks many layers while selecting good dies, must be evaluated separately.
In the race to mass production, processes that repeat the same bonding quality matter
Applied Materials and Besi announced an expanded partnership in advanced packaging on October 1.
Since 2020, the two companies have combined Applied Materials' process technologies, such as polishing, cleaning and metrology, with Besi's chip placement and bonding technology. One result is Kinex, an integrated die-to-wafer hybrid bonding system.
It is designed so that surface preparation before bonding and the actual chip attachment step work as one.
The direction of this equipment development shows that what matters in hybrid bonding is not only how precisely chips can be aligned, but also how reliably the same bonding quality can be repeated in a mass-production process.
However, the partnership announcement does not support the conclusion that Samsung or SK hynix has adopted Kinex.
The joint research the two companies are expanding covers not only hybrid bonding but also improvements to existing TCB technology.
In other words, the path of continuing to improve existing methods and the path of moving to new hybrid bonding are proceeding in parallel.
SK hynix's shipment of HBM4E samples using Advanced MR-MUF is also an example of advancing a next-generation product without waiting for a full shift to hybrid bonding.
What this shows is that the timing of adopting a new bonding method is not determined by technological novelty alone.
If existing processes can meet the capacity and thermal performance customers demand, there is value in continuing to use accumulated mass-production know-how.
On the other hand, as chip warping and heat dissipation constraints tighten with more layers, the advantage of hybrid bonding, which can reduce the thickness between layers, grows.
However, this general view of technology choices cannot be used to explain SK hynix's development delay as the result of a deliberate strategy.
If Samsung has in fact shipped hybrid-bonded samples to customers first, it has the advantage of evaluating them in customer environments and identifying mass-production challenges early.
Still, between a prototype that works and the ability to supply the volumes customers need reliably, the challenges of yield and manufacturing time remain.
Beyond post-stacking reliability, whether the product works properly in the final package combined with an AI processor will also be an important factor in adoption decisions.
Going forward, the key factors in judging the gap between the two companies are the HBM generation and layer count that use hybrid bonding, when customer qualification is completed, and the yield and supply volume that can be secured in mass production.
A manufacturer that meets these conditions can fit more memory into the same package height, widening its options for meeting the ever-growing capacity demands of AI models.