In the race to shrink chips, it can look as if the company that adopts the newest lithography tool first takes the lead. Yet with ASML's High-NA EUV, reported to cost as much as $400 million per tool, TSMC and Samsung continue research evaluations while pushing volume adoption further out. Intel, which is working to regain leadership in process technology, has already started using it on some 18A products. The reversal has less to do with resolution than with the cost of discarding existing processes and the value of gaining production data early. The price of a single tool does not capture what matters: the economics per good wafer. That is the lens for reading the three companies' decisions.
"Adoption" has three stages: delivery, limited production, and full design
ASML divides High-NA EUV customer adoption into three stages. Stage one is evaluation, with an EXE:5000 placed in an R&D facility. Stage two, in 2026–2027, is operation on one or two layers to confirm production readiness. Stage three is design-in and production on critical layers of leading-edge nodes. Counting a company that has taken delivery of a tool and one that uses it in a product's production flow as equally "adopted" leads to misreading each company's decision.
In stage one, companies check whether the resist can form the intended shapes, whether mask defects can be inspected, and whether existing metrology tools can control dimensions and overlay. Exposing product wafers does not necessarily mean the technology has been adopted in the standard flow for chips that are sold. Moving to stage two raises questions about uptime over long runs, maintenance, lot-to-lot repeatability, and connections to upstream and downstream processes. In stage three, design rules and mask sets are optimized on the assumption of High-NA, so the cost of backing out becomes large.
TSMC and Samsung have publicly described stage-one activity. TSMC's annual report mentions development of High-NA lithography, and ASML has cited a Samsung evaluation in which cycle time was shortened. What both are waiting for is not the start of research but the point at which a volume node is designed around High-NA. Intel 18A, by contrast, is closer to stage two: it does not switch the whole flow, but dual-qualifies specific layers on both High-NA and the existing NXE. The three companies should be compared by how much production responsibility they have given the tool, not by how new the tool they bought is.
What 0.55 NA reduces, and the other burdens it adds
The "NA" in High-NA is the numerical aperture of the projection optics. The EUV wavelength is the same 13.5 nm as in earlier tools, but raising NA from 0.33 to 0.55 lets the system form finer images on the wafer. ASML's stated resolution is 8 nm for EXE versus 13 nm for the current NXE. A single exposure can handle features 1.7 times smaller, and in theory 2.9 times the two-dimensional density, with 40% higher image contrast. The 40% figure refers to the light-dark difference in the exposed image; it does not mean chip yield rises by 40%.
When fine interconnects are made with a conventional tool, one layer is split across multiple masks. Exposure is combined with deposition and etch, and cleaning and metrology are repeated, which is multi-patterning. For the densest interconnect layers assumed in the A14/A10 generation, imec explains that a feature requiring three to four masks at 0.33 NA can be formed in one exposure at 0.55 NA. ASML likewise cites a customer case in which one High-NA exposure replaced three to four Low-NA exposures, and in some critical layers up to 100 process steps fell to 10. Even if the exposure tool is expensive, total cost can fall for layers where it eliminates many steps before and after.
In exchange, the 0.55 NA optics come with a half-field constraint. Where conventional tools expose up to 26×33 mm² at once, EXE exposes 26×16.5 mm², so more exposures are needed to cover a wafer. For large AI chips, stitching two exposure fields together, or splitting the design, may be required. Depth of focus and stochastic microdefects affect production cost. So does the maturity of High-NA masks, resists, inspection, and metrology.
To use a city-road analogy, layers stacked with multi-patterning are congested intersections, and High-NA is like replacing one with a grade-separated interchange. Rather than elevating every road, it is cheaper to start with the intersections where the effect is greatest. But semiconductor layers are tied to earlier and later layers through overlay, etch, and design rules. They cannot be swapped out as independently as road intersections, and even limited adoption requires requalifying the whole product flow, which is where the analogy breaks down.
Heavier than $400 million: the math on one finished wafer
Reuters reported that a High-NA tool costs up to about $400 million. Depending on exchange rates, that is tens of billions of yen, and about double the price of current EUV. ASML does not publish a price list, so $400 million is a reported figure, not a list price. A fab's comparison goes far beyond the purchase price. Tool depreciation is added to materials such as masks and resists and to process costs for deposition, etch, and cleaning. Inspection labor and equipment, floor space, power, work-in-process inventory, and wafers lost to defects are included too, and the total is divided by the quantity ultimately sold as good product.
The speed of the tool alone also does not translate into the speed of the manufacturing line. ASML cites throughput of 175 wafers per hour for the EXE:5200B and 230 wafers per hour for the current NXE:3800E, so on a single scanner Low-NA is faster. But if a layer is exposed three times on NXE, with a return to upstream and downstream processes each time, the time to completion and the number of tools needed both grow. If one EXE exposure can replace those, productivity measured in finished layers or good wafers can reverse even with fewer wafers per hour.
| Source of cost | Extending Low-NA | Switching to High-NA |
|---|---|---|
| Exposure and adjacent steps | The more multiple exposures, the more masks, deposition/etch steps, and metrology | Steps can be cut on layers that become single exposure |
| Tools and operations | Existing tool fleet, maintenance, people, and recipes can be reused | Bears the cost of expensive new tools, half-field, and low utilization during ramp-up |
| Yield and time | Each added step adds defect opportunities and work-in-process time | Fewer steps, but new materials and overlay must be learned |
ASML says cumulative High-NA wafer throughput exceeded 500,000 as of April 2026 and availability has risen above 80%. Samsung's cycle-time reduction in one application was 60%. Both indicate production feasibility, but neither guarantees the same improvement for every layer, product, and fab. Moving layers that are less dense, and where a single Low-NA exposure suffices, to High-NA would only add tool cost and the half-field penalty. Layers are chosen not by whether they can be resolved, but by whether the value of the steps that can be eliminated exceeds the cost of switching.
The strength of TSMC and Samsung: they can keep extending existing EUV
TSMC shipped 15 million 12-inch-equivalent wafers in 2025, with annual capacity above 17 million, and 7 nm and below accounted for 74% of wafer revenue. At that scale, the existing NXE fleet, mask supply, and process recipes form an enormous production system, tied to design assets, spare parts, and engineers' experience. As long as the next node can be built with Low-NA multi-patterning, there is great value in using those assets to the fullest.
In TSMC's 2026 roadmap, N2U is scheduled for volume production in 2028 and A12 and A13 in 2029. A13 shrinks area by 6% from A14 while promising full backward compatibility of design rules. Reuters reported that the technologies shown at the symposium do not use High-NA and that the plan is to keep using current EUV for the next several generations. TSMC's own official materials do not state the exposure method, and the company has not officially declared that it will not adopt High-NA through A13. Even so, if shrinks with preserved compatibility and good yield can be achieved, the urgency of moving the production base to a new exposure system falls.
Samsung is also evaluating High-NA. ASML has presented its results, so research has not stopped. Meanwhile, Park Chang-min of Samsung's semiconductor research institute said in August 2026 that the company had wanted to apply it in volume production at 2 nm and 1.4 nm but that technical supplements were needed, that 0.33 NA multi-patterning would be mainstream through 1.4 nm and 1 nm, and that High-NA would be needed from A10 and below. "Around 2030" is ZDNet Korea's observation based on the company's roadmap, not a timeline Samsung has committed to.
Samsung is mass-producing first-generation 2 nm GAA and developing second-generation 2 nm and 1.4 nm. Overlapping the ramp of a new transistor structure with the ramp of High-NA-related processes in the same product generation makes it harder to isolate the cause of problems. Stabilizing the current GAA process while accumulating High-NA research data, then moving to volume production starting with layers where the benefit of fewer steps is large enough, leaves fewer variables to control. This explanation is not one Samsung has published as a reason for delay; it is an economic interpretation drawn from its engineers' remarks and production plans.
The waiting at TSMC and Samsung is not a judgment that High-NA is unnecessary. They place the point where the added-step cost of Low-NA exceeds the switching cost of High-NA at a finer node. The longer a company can extend existing technology, the less it needs to hurry with new tools. The caution of the leaders reflects the breadth of options they have rather than any shortfall in scaling capability.
Intel is buying learning time before it buys tools
The Intel production case ASML confirmed on July 15, 2026 is not a full migration of the 18A flow. It covers specific layers in some products of Core Ultra Series 3, codenamed Panther Lake, qualified on both High-NA EXE and conventional NXE in a production line in Oregon. Yield on the High-NA side matched the NXE side, and the products involved have shipped, but layer names, layer counts, wafer share, and SKUs have not been disclosed. Overall product yield is also undisclosed.
Dual qualification costs money. Even so, keeping mature NXE as the main supply line while sending suitable lots to High-NA reduces the risk that a stoppage of the new tool or process variation spreads to the entire product supply. At the same time, it lets Intel learn about long-term operation, maintenance, and lot-to-lot variation, which test wafers alone make hard to learn. Product-specific defects and interactions with upstream and downstream processes also become easier to see from production data. ASML likewise says data from 18A will be used to improve tool setup, availability, and methods for production implementation.
For Intel, this learning serves as insurance for 14A, which is scheduled to ramp into volume production in 2028. In imec's example conditions for the A14/A10 generation, three to four Low-NA masks on the densest interconnect layers could be replaced by a single High-NA exposure. If Intel narrows the target layers on 18A and experiences the problems there, it can more easily decide which layers to adopt, how many tools are needed, and how much spare capacity to hold, from measured values by the time 14A design rules are fixed. Mask and resist conditions can also reflect production data. The limited use on 18A can be read not as an investment to minimize current manufacturing cost alone, but as an investment that buys options to lower the probability of failure at the next node.
This time value is not equal across the three companies. TSMC has the option of extending a proven Low-NA process and can keep producing customer products while it waits. Intel is still on the way to regaining process leadership and the trust of foundry customers, and the experience of running High-NA on real products itself reduces 14A ramp risk and uncertainty in its explanations to customers. Amortizing an expensive tool requires sufficient wafer volume, and Intel itself has disclosed that leading-edge node economics need volume beyond its internal products. Early adoption is not a universal comeback play; it is also a bet whose value grows if 14A wins external customer volume.
Three observed values will move the timing of adoption
In High-NA adoption news, three numbers matter more than the number of tools delivered. The first is the number of layers qualified for production. The stage two ASML describes is only readiness confirmation on one or two layers, and there is a distance between that and stage three, where it is broadly built into design rules and mask sets. Since the number of Intel 18A layers is undisclosed, one cannot go so far as to say 18A has become a High-NA node.
The second is the total number of process steps and the cycle time to complete a layer, rather than the number of exposures. Even if three to four Low-NA exposures become one High-NA exposure, the benefit shrinks if additional metrology, defect repair, and stitching increase. Whether the 60% reduction shown in one Samsung application is reproduced across multiple products and long-term operation will affect production ROI.
The third is throughput at practical dose, availability, and good-die yield. Availability above 80% for High-NA is progress, but in a giant fab, downtime leaves expensive tools and downstream processes idle. Beyond the EXE's 175-wafers-per-hour tool spec, one needs to track the number of finished wafers after multi-patterning is removed, and the number of sellable die.
If these three improve, the adoption timing set by TSMC and Samsung could be brought forward. Conversely, if improvements in Low-NA throughput and multi-patterning technology outpace the maturing of High-NA's surrounding processes, the wait will lengthen. The fact that Intel uses it first does not contradict TSMC's and Samsung's ability to mass-produce leading-edge nodes. What each company is maximizing differs: for Intel it is learning time until the next generation, and for TSMC and Samsung it is revenue per good wafer, including mature assets.