IBM, the Quantum Science Center (QSC) at Oak Ridge National Laboratory (ORNL) and AMD announced on November 5, 2026 a co-design platform for studying how to detect and correct errors in quantum computers. At IBM's site in Poughkeepsie, New York, the platform places the 120-qubit quantum processor "Nighthawk r2" alongside "Umbra," a computing system equipped with CPUs and GPUs.
Quantum error correction requires not only the hardware that runs the qubits but also a conventional computer to process the measurement results. The new platform is meant to test that combination in a single research environment. The central challenge is balancing the ability to handle large volumes of computation with the ability to respond immediately after a measurement. IBM's announcement and technical explainer describe the configuration.
Quantum hardware and Umbra in one research environment
According to IBM's technical explainer, researchers previously had to link cloud-based quantum devices to a separate classical computing system themselves, using APIs. Classical computing here means ordinary computation on CPUs and GPUs. In the new setup, the quantum and classical sides sit at the same site, providing a shared environment in which hardware and software can be combined to evaluate different approaches.
Umbra is equipped with AMD's "Instinct MI355X" GPUs and 5th Gen "EPYC" CPUs. Reuters also reported on November 5 that the platform combines quantum devices with Umbra to test ways of detecting and correcting errors. The co-design effort involves advancing design and evaluation while reconciling the requirements of each type of hardware.
Note, however, that the figure of 120 for Nighthawk refers to the number of physical qubits that make up the device. It does not mean that 120 logical qubits, with information protected from errors, are available. The scale of the hardware and how well information can be protected after correction need to be read as separate matters.
Two kinds of speed that error correction demands
Quantum error correction spreads information across multiple qubits and checks them repeatedly. The software that infers where and what kind of error occurred from that check data is called a decoder. To keep up with the quantum processor, the time between receiving the check results and reaching a decision must also be short.
Meanwhile, training decoders and evaluating them at larger scales call for computing power capable of processing large amounts of data.
The classical computing that supports quantum error correction therefore has two different requirements: a quick response following measurement, and parallel processing for large volumes of data.
Comparing IBM's platform explainer with AMD's description of use cases, both published November 5, yields the following summary. Which components are installed is based on IBM's announcement.
| Hardware or software | Use described in the sources | What can be confirmed for Umbra |
|---|---|---|
| 5th Gen EPYC CPU | Orchestration and general-purpose computing | Installation stated |
| Instinct MI355X GPU | Simulation, optimization and parallel scientific computing. IBM also describes exploring low-latency decoding on GPUs | Installation stated. Achieved performance for each use not disclosed |
| Versal adaptive SoC | Low-latency control, readout and decoding | General AMD product use. Installation in this platform not stated |
| ROCm | Software foundation supporting high-performance computing, AI and device connectivity | General AMD description. Adoption in this platform not stated |
This table is not a performance comparison of products; it organizes the uses of each processing type. Because GPUs are also being explored for low-latency decoding, their role cannot be fixed as "dedicated to parallel computing." Nor is there any basis for adding the Versal and ROCm products AMD describes to the list of what is installed in Umbra. Absolute latency figures and decoding performance comparisons have not been disclosed in this announcement.
What to measure to see the platform's effect
The key to co-design is not treating classical computing speed as a single performance number, but evaluating which processing runs under which time constraints.
IBM's "Quantum System API" handles mid-circuit measurement of qubits and real-time actions based on the results. Signal timing can be specified, and the actual executed content and raw measurement signals can reportedly be accessed. In other words, everything from obtaining check data to acting on the results can be tested as one continuous process.
IBM also listed as evaluation targets the number of qubits, time and trial samples each approach requires, as well as how many classical computing resources it uses. QSC Director Travis Humble said in IBM's announcement that Umbra will let researchers "test new ideas and scale up to evaluate approaches." His remark concerns future research.
What has been released is a description of the research platform in an official announcement and a technical blog. It is not a new peer-reviewed paper showing improved correction performance. The logical error rate, which expresses how often errors remain in logical information, the number of trials for specific correction methods and the number of correction cycles are not given, and no latency comparison results have been presented.
The co-location of the facilities is confirmed. But the materials contain no experimental or simulated values showing how much performance improves as a result, and no independent replication has been presented. The announcement cannot be treated as research verifying a causal relationship or correlation between the arrangement and performance.
An evaluation environment aimed at 2028 goals
IBM's announcement cited the U.S. Department of Energy's (DOE) "Q Competition" targets for the end of 2028: 100 logical qubits and 100,000 operations it calls "hard operations." Logical qubits, the unit of protected information, and Nighthawk's 120 physical qubits are not numbers that can be compared directly by size. The joint platform is positioned as an environment for testing correction approaches and how to use computing resources toward that goal.
There are also plans to connect it to ORNL's high-performance computing facility, the Oak Ridge Leadership Computing Facility (OLCF). Both IBM's announcement and Reuters' report describe it as a future connection, not an announcement that the connection has already been completed.
The next useful evidence will be results comparing combinations of correction approaches and classical computing resources under the same execution conditions. Does the response after measurement fit within the required time? How does the computational burden change as scale increases? Such comparisons would reveal the conditions needed to keep error correction running, which qubit counts and GPU scale alone cannot show.