Intel Foundry has said it is making version 0.9 of the process design kit (PDK) for its next-generation manufacturing process, Intel 14A, broadly available to customers, according to an official Q&A dated November 2, 2026. Intel explained in its October 29 earnings briefing that it had begun early provision to select customers earlier that month, so the latest step appears to widen the audience. Customers can now use models validated on actual manufactured silicon to move ahead with physical design work such as circuit placement and routing.
In Intel 14A, not only the transistor structure but also the placement of power wiring and the height of standard cells affect circuit design. The key point of PDK 0.9 is that it lets designers evaluate how these design choices affect performance, power consumption, and area, using models that reflect the characteristics of the actual manufacturing process.
Using models validated on real silicon for physical design
A PDK compiles a semiconductor manufacturing process's design rules and electrical characteristics so they can be used in electronic design automation (EDA) tools. For example, design rules define how close wires can be placed to one another, while device models describe the current characteristics of a transistor when voltage is applied. EDA tools use this information to verify that circuit placement and routing satisfy manufacturing constraints, and to simulate whether the designed circuit will work as intended.
Even wiring that meets manufacturing rules inevitably has electrical resistance and parasitic capacitance with neighboring wires. Extracting these parasitic elements from the layout makes it possible to evaluate signal delays that are hard to see from a circuit schematic alone. For example, when there is insufficient timing margin for a signal to propagate within a clock cycle, designers can compare two approaches: changing the placement to shorten the wiring, or swapping in a standard cell with stronger drive. Meeting manufacturing constraints and achieving the required operating speed must be verified separately.
According to Intel, each PDK for 14A is built on silicon-validated results, and with each successive version it reflects the characteristics of the manufacturing process more accurately and comprehensively. For many customers, Intel says, PDK 0.9 serves as the benchmark for deciding to begin serious product design. By proceeding with design before process qualification is complete, the aim is to be able to hand design data over to manufacturing in step with the qualification schedule. Even when models are based on measured values, however, the final product's operating frequency will vary depending on the circuit architecture, placement, routing, and other factors.
Actual design work also requires compatible EDA tools and design IP in addition to the PDK. EDA tools handle circuit placement, routing, and verification, while design IP supplies reusable circuit blocks to incorporate into products. Intel says certification of design tools from multiple EDA vendors is progressing, and it plans to keep validating tools, IP, and design flows ahead of future PDK updates. For customers, what matters is whether the combination of tools and IP they use can carry them smoothly through the necessary design steps.
How RibbonFET 2, backside power, and Turbo Cells change design
Intel 14A builds on manufacturing technology developed in the previous generation and adopts RibbonFET 2, a second-generation gate-all-around (GAA) transistor, along with PowerDirect, a new backside power delivery technology. A GAA transistor has a structure in which the gate surrounds the channel through which current flows, and the gate voltage controls that current. Circuit designers use models that reflect the electrical characteristics of this structure to evaluate operating speed and power consumption.
PowerDirect changes the path by which power is delivered inside the chip. Placing power wiring on the back side of the wafer makes it easier to free up space in the front-side wiring layers for signal routing. Even in densely packed areas of a circuit, this gives more freedom for signal routing, though the benefit varies with the actual placement and routing. For that reason, designers need to place circuits according to the design rules and then evaluate routing congestion and signal delay.
Intel 14A also offers high-drive standard cells called Turbo Cells. Standard cells are standardized basic circuits such as logic gates, and they are used for automated placement and routing by EDA tools. According to Intel's technical materials for HPC and AI, Turbo Cells use the height of two rows of ordinary standard-cell placement to obtain a larger drive current. In circuits with heavy wiring or large load capacitance at the connection destination, increasing drive current can shorten signal switching time.
However, because Turbo Cells need a larger placement area than ordinary cells, they are not something to be adopted across an entire chip. They need to be applied where shortening delay matters, such as critical paths that limit operating frequency, while balancing area and power consumption. There is little reason to replace even circuits with ample timing margin with high-drive cells. Whether designers can optimize performance, power, and area (PPA) by combining the routing space made available by PowerDirect with the strong drive of Turbo Cells is a key design consideration.
PDK 1.0 planned for Q1 2027; production capacity expansion depends on customer demand
According to Intel's Q3 2026 earnings materials, its quarterly report, and the official Q&A, version 0.9 of the Intel 14A PDK was provided to select customers in October 2026, and version 1.0 is scheduled for the first quarter of 2027. The company is also continuing to invest toward risk production in 2027, but says it will decide how much and how quickly to expand manufacturing capacity based on committed customer demand. That demand includes both Intel's own products and those of external customers. Risk production refers to the stage ahead of full-scale volume production in which manufacturing conditions, yield, product quality, and other factors are checked.
Process qualification confirms that the process meets specified technical and quality standards. The volume production stage, by contrast, requires the ability to stably manufacture the needed quantity of chips that meet quality requirements. Intel explains that 14A development is approaching the performance and yield levels the industry expects, but the Q&A does not disclose specific yield figures or operating frequencies demonstrated in customer products.
Intel also revealed in its quarterly report that it decided in the second quarter of 2026 to complete development of 14A. However, neither the broader PDK availability nor the development decision means that volume production for external customers is starting right away. Going forward, the focus will be on how far process qualification progresses, when customers move their designs into manufacturing, and whether Intel can secure enough committed demand to justify capital investment. The materials do not disclose per-customer production start dates or details of volume production contracts, so these points will need continued monitoring to judge the scale and timing of Intel 14A's commercial rollout.