Intel Foundry has shipped some units of Intel Core Ultra Series 3 (development codename Panther Lake) manufactured using ASML's High-NA EUV lithography systems to customers. On July 15, 2026, ASML announced that this marks the industry's first customer shipment of a mass-produced logic product manufactured using High-NA EUV. PCs featuring Panther Lake have been on sale worldwide since January 27, so this is not a matter of prototyping for future products. However, what has been confirmed applies only to a portion of the product lineup and to specific layers within Intel 18A. Intel has not switched all of 18A over to the new equipment at once; rather, it has gained the option to manufacture the same layers using either conventional EUV or High-NA EUV.
A Portion of Panther Lake, Specific Layers of 18A
ASML's announcement contains three qualifications that define the scope of High-NA EUV's application. The target is "some" of Panther Lake, the equipment was used for "specific layers" of 18A, and the qualification location was Oregon. Products manufactured using High-NA EUV have been shipped to customers, and their yield reportedly reached parity with the conventional 0.33NA EUV "NXE" platform. However, actual yield figures, layer names, target SKUs, and the proportion of total shipments have not been disclosed.
The term "dual qualification" captures the significance of this announcement well. If the same design layer can be manufactured using both High-NA EUV's "EXE" and the conventional NXE, Intel gains the flexibility to select the process based on equipment availability and factory production planning. This allows Intel to collect data on setup times, utilization rates, and process integration from actual products while minimizing the risk that downtime or adjustments to the new equipment would immediately halt 18A shipments.
Intel's product database lists 17 Panther Lake products. Most launched in Q1 2026, with the Intel Arc G3 series for handheld gaming PCs following in Q2. However, which specific products went through High-NA EUV has not been disclosed. Interpreting this as the emergence of a unified "High-NA-manufactured Panther Lake" product category would go beyond what the announcement actually states.
How 0.55NA Reduces Multi-Patterning
High-NA EUV does not change the wavelength of light used for exposure, but instead increases the numerical aperture—a measure of the optical system's light-gathering capability—from 0.33 to 0.55. ASML's EXE:5000 and its mass-production successor, the EXE:5200B, offer 8nm resolution, delivering 40% higher imaging contrast than the NXE. According to ASML, this allows features formed in a single exposure to be 1.7 times finer, theoretically supporting 2.9 times the transistor density. This figure represents the equipment's capability—it does not mean that Panther Lake itself achieves 2.9 times the density of previous products.
Being able to print fine patterns in a single exposure reduces the need for multi-patterning, where the same layer is exposed multiple times. During its Q1 2025 earnings call, ASML reported that Intel had exposed over 30,000 wafers per quarter using High-NA equipment, and for one particular layer, had reduced a process that previously required more than 40 steps down to fewer than 10. Shortening the process also reduces the time a wafer spends within the fab, decreasing the opportunities to pick up defects at each step. However, it has not been disclosed whether this test layer is the same as the layer applied to the products shipped this time. What has been confirmed is that Intel achieved NXE-comparable yield on a specific layer using High-NA EUV and shipped the resulting products to customers.
Higher resolution does not automatically translate into lower mass-production costs. Because the EXE uses anamorphic optics, the area that can be exposed in a single pass is half that of the NXE. ASML compensates for this by speeding up the wafer stage and the reticle stage that moves the mask, thereby boosting productivity. Additionally, masks and photoresists must be optimized, and conditions from metrology through etching need to be adapted to the new system.
In 2025, research organization imec confirmed electrical yields exceeding 90% on two test structures for 20nm-pitch metal interconnects created via single exposure with High-NA EUV. Meanwhile, a 2026 technical review identified remaining challenges including improvements to depth of focus, suppression of stochastically occurring defects, and stitching between exposure fields. There remains a gap between an exposure tool's ability to print lines and the ability to consistently and affordably mass-produce commercial chips—a gap that requires further refinement of materials and surrounding processes.
Still in Stage Two of ASML's Three-Stage Rollout
ASML has described the introduction of High-NA EUV in terms of three stages. In Stage 1, customers install the equipment in R&D facilities to evaluate its capabilities. In Stage 2, expected to run from 2026 to 2027, customers run one or two layers through the equipment to verify production readiness. In Stage 3, High-NA EUV is incorporated into the design phase for critical layers at leading-edge nodes and enters full-scale mass production.
The "dual qualification of specific layers" confirmed this time aligns closely with Stage 2. Even though mass-produced products shipped to customers were used, this is not an announcement that Intel has designed all critical layers of 18A around High-NA from the outset. ASML itself stated during its July 15 earnings call that the platform's maturity is approaching—but not yet at—the level required for full mass-production deployment. The term "mass-produced product" and the fact that technology adoption remains selective are not mutually exclusive.
The equipment's footprint also remains in early stages. According to ASML's 2026 shareholder meeting materials, 8 High-NA units had shipped by the end of 2025, with 6 in operation. The company has indicated a timeline of meeting mass-production requirements by the end of 2026, with customer adoption expected in 2027-2028. Intel has moved ahead of this timeline by demonstrating the technology using products actually sold to customers, but this does not represent an industry-wide, simultaneous shift to EXE.
Qualification in Oregon, Mass Production in Arizona
Examining the manufacturing sites separately clarifies Intel's strategy. In 2024, Intel installed its first commercial High-NA EUV system, the EXE:5000, at its D1X R&D facility in Hillsboro, Oregon, and began calibration. At the time, the plan was to advance product-based demonstrations using 18A while reserving High-NA EUV for mass production on the next-generation Intel 14A. The dual qualification confirmed by ASML this time was also carried out in Oregon.
Meanwhile, the facility Intel has publicly identified as the standard mass-production site for Panther Lake is Fab 52 in Chandler, Arizona. Intel has explained that it develops 18A in Oregon, completing manufacturing qualification and initial production there, before scaling up mass production at Fab 52. The July 15 announcement does not state that High-NA EUV has been introduced at Fab 52. What can be confirmed is only that some Panther Lake units that passed through EXE in Oregon achieved NXE-comparable yield and reached customers.
This division of labor also serves as a mechanism for Intel to test new processes at its R&D facility and gather product and process data before transferring them to mass-production fabs. Simply installing equipment does not complete the transfer. Each fab must independently raise equipment utilization rates, align mask and resist conditions, and reproduce the entire process including inspection and correction. Whether the data gained from 18A can be reflected in the design rules and production flow for 14A will determine whether Intel's upfront investment pays off.
Even With Mass-Produced Products Shipping, 0.33NA EUV Remains the Workhorse
Looking at ASML's equipment sales further clarifies where High-NA EUV currently stands. System revenue for Q2 2026 included just one High-NA unit. Meanwhile, the company expects to ship approximately 65 conventional Low-NA EUV systems throughout all of 2026. The immediate task of expanding production capacity for leading-edge logic and DRAM still falls to the NXE.
This is precisely why Intel's dual-qualification approach holds practical value. It allows Intel to test process shortening using EXE's higher resolution while keeping the existing fleet of NXE systems as the core of supply. The question surrounding High-NA EUV adoption has shifted from "can it achieve finer patterning?" to a calculation of how far process steps and cycle times can be reduced. Layers must also be selected where the benefits of reduced defects outweigh the equipment costs.
The next figures Intel and ASML should disclose are the scope of layers and SKUs passing through High-NA EUV, EXE utilization rates, and manufacturing costs relative to the NXE. It would also be worth confirming whether processes developed in Oregon will be transferred to other facilities, and whether Intel will advance to Stage 3—designing critical layers around High-NA from the start—for 14A. Neither equipment costs nor manufacturing costs have been disclosed at this time. For the customer shipments that have begun with a portion of Panther Lake to expand further, EXE will need to maintain NXE-comparable yields, and cost savings from shortened processes will need to exceed the additional expenses associated with the equipment and surrounding processes.