Intel is building up its sales organization to win more orders for custom chips made to each customer's specifications. On August 7, the company announced the hiring of Dean Jarnac, formerly chief commercial officer at Marvell, and explicitly named ASICs (application-specific integrated circuits) as part of his remit. On October 8, CRN reported analyst Jack Gold's view that Jarnac's experience could help grow the custom chip business and could also lead to orders for Intel Foundry. Intel has the means to handle everything from design to manufacturing, but there are still conditions to meet between a customer asking Intel to develop a custom chip and that customer choosing Intel's factories.
A former Marvell sales chief to sell something other than off-the-shelf products
At Marvell, Jarnac oversaw global sales as well as the division that technically supports customer designs, along with sales operations. He has also held senior sales roles at Broadcom and AMD, and at Intel he will report directly to CEO Lip-Bu Tan. Intel said in its August announcement that he would join in September, and it listed PC and data center products among his areas of responsibility. This is not the appointment of a technical lead who would head only ASICs; it is a change in sales leadership spanning existing products and a new business.
Selling custom chips involves different work from pitching a finished CPU for a customer's servers. Intel has to understand the work the customer wants to process and be involved from the stage of turning those requirements into circuits. How much the customer designs itself, and which circuits the semiconductor company provides, affects both development costs and supply terms.
In its report for the quarter ended August 1, 2026, Marvell explained that customers go through a long selection process before a design is adopted, and that once a competitor is adopted first, switching costs and risks rise for the customer. The point at which sales gets involved can also determine whether an order is won.
Intel had already put its design organization in place. In September 2025, it announced a central engineering group centered on Srini Iyengar, who came from Cadence, to build a custom chip business for external customers. The idea is to pair engineers who build customer-specific circuits with sales experience in assembling development projects with customers. That complementary role is why Jarnac's hiring is tied to the ASIC strategy.
Still, having deep customer relationships is not the same as being chosen to build a customer's next-generation chip. Orders come closer only when design support capability is tied to the delivery schedules and supply that customers need. It is too early to assume that a single sales executive's move will shift Marvell's business to Intel.
Different kinds of orders in the Google and Fortinet deals
The custom chip collaborations Intel has already announced are not limited to large AI accelerators. A partnership announced with Google on April 9 includes expanding joint development of ASIC-based IPUs. An IPU is a chip that takes over networking, storage, and security processing from the CPU, making a data center's computing resources easier to use. Its purpose differs from that of Google's AI compute chip, the TPU.
On July 21, Intel announced a collaboration to co-develop Fortinet's next-generation security processor, the SP6. It combines Fortinet's knowledge of dedicated security chips with Intel's design, packaging, and manufacturing capabilities, and the announcement explicitly cites diversifying the supply chain as an aim. Intel supports the development of a chip tailored to Fortinet's use across several stages of the process.
| Announced project | Announcement date | Workload addressed | Collaboration scope stated | Process node / volume timing |
|---|---|---|---|---|
| Google IPU | April 9, 2026 | Networking, storage, security | Expanded joint development of ASIC-based IPUs | Neither stated |
| Fortinet SP6 | July 21, 2026 | Dedicated security processing | Co-development combining Intel's design, packaging, and manufacturing capabilities | Neither stated |
The table lines up the workload, collaboration scope, and undisclosed items from the text of Intel's announcements. It is not a comparison of performance or sales scale.
The Google IPU involves joint design, while the Fortinet SP6 collaboration covers design, packaging, and manufacturing, but neither announcement states a process node or volume production timing. Given that, the SP6 can be read as a concrete example of Intel combining multiple stages, but it does not prove that Intel has won a customer that will build in volume on a specific leading-edge process.
Reading ASIC as a synonym for AI accelerator would misjudge the market Intel is now reaching into. The IPU is for infrastructure processing and the SP6 is for security, each with a clear use on the customer side. What Intel is trying to expand is the work of building chips for such individual uses, and which stages it is entrusted with will shape Foundry's growth.
The advantage of owning factories, and the difficulty of changing where chips are made
Marvell has no wafer fabrication, assembly, or packaging facilities of its own and relies on external manufacturers. Its quarterly report states that TSMC is its sole supplier for leading-edge process wafers. Its business is to deliver chips to customers by providing design and circuits and coordinating with outside factories. Intel differs in that it can build its own manufacturing capacity into the same proposal.
But a customer choosing Intel's design support does not mean manufacturing will follow to Intel. Marvell's same report explains that it designs standard products for a specific process at a specific factory, and that moving production to another factory is difficult and could significantly delay securing supply. The place of manufacture is not something easily switched on commercial terms after design has progressed.
If Intel wants to increase the number of projects built in its own factories, it must show the advantages of its manufacturing process before a customer's design is fixed. Customers weigh not only circuit performance and power consumption but also the outlook for moving from prototype to volume production. The experience Jarnac gained working on customers' development at Marvell could be useful at these early stages of choice. However, that experience alone does not prove process suitability or volume production capability.
Intel also has room to win orders for advanced packaging, separate from the factories that make the chips. EMIB embeds a small silicon bridge in the substrate to connect multiple chips, and is also used to connect compute chips to high-bandwidth memory (HBM). On its official page, Intel cites a volume production track record using silicon made both in-house and externally. One conceivable path is to leave the compute chip's manufacturer unchanged while entrusting assembly to Intel.
EMIB-T adds through-silicon vias (TSVs) to that bridge. Intel suggests it may make it easier to integrate circuits from other package designs. That gives Intel more options to offer on the packaging side, separate from changes to wafer manufacturing. However, it has not been announced that Google's IPU or Fortinet's SP6 will use EMIB-T.
Winning design support work, assembling packages for externally made chips, and fabricating wafers in its own factories are each business opportunities for Intel, but adoption of its advanced packaging cannot be read as adoption of Intel's manufacturing process. It is necessary to distinguish how much of the work a given project actually entrusts to Intel.
ASICs nearing $2 billion: volume production and profitability come next
According to CRN, CFO David Zinsner said on the July 23 earnings call that the ASIC business is approaching an annualized revenue scale of $2 billion and that he believes it will reach $4 billion in the not-too-distant future. Management's expectations for custom chips as a growth business are high. However, the $2 billion figure is not confirmed annual revenue, and no deadline has been given for reaching $4 billion.
Nor can this business scale be taken as revenue Intel Foundry has earned from external wafer manufacturing. Design support and custom chip sales represent different work from contract manufacturing in terms of revenue. Intel's second-quarter earnings materials also state that segment revenue including Foundry includes intersegment transactions. Whether the business as a whole has grown and whether outside customers have chosen the factories must be checked separately.
Custom chips also face the challenge of recovering up-front development costs. In its ASIC business, Marvell describes a structure in which customers pay up-front development costs according to development milestones, and it discloses that profitability could worsen if those payments fall short or sales volumes are insufficient. This does not mean Intel's contracts have the same terms, but it is a reason to separate getting a design adopted from earning a profit in volume production.
The sales Jarnac will lead include turning customers' ideas into development projects. Beyond that, the question is whether engineers and the manufacturing division can advance prototypes and supply the quantities customers need. Intel's strength is that it can propose multiple stages of the process, but customers are under no obligation to choose all of them as a package.
In future project announcements, it will be worth watching whether the stages Intel is entrusted with and the process nodes become specific. If volume production timing and actual shipments follow, there will be enough evidence to judge that the stronger ASIC sales effort has also led to external orders for the factories. Building up projects that can steadily supply customer-specific chips and recover development costs is the condition for turning Intel's strategy of linking design and manufacturing into a sustained business.