Intel has revealed a concept for future AI chip packages that would incorporate more than 70 silicon bridges. According to ZDNet Korea, Kyuoh Lee, director of packaging at Intel Foundry, described a large 240×240mm package concept on November 4 at ISMP 2026, a semiconductor packaging conference held in Busan, South Korea. A silicon bridge is a component that connects multiple chips within the same package at high density, and its importance grows as more compute chips and high-bandwidth memory (HBM) stacks are added. However, no timeline has been given for mass production of configurations using more than 70 bridges, and challenges remain in manufacturing capacity and materials supply before such products could actually ship.
A Large Package Concept With 32+ HBM Stacks and 70+ EMIB Bridges
In the future concept Lee presented, a 240×240mm package would carry 32 or more HBM stacks and 70 or more EMIB bridges. EMIB (Embedded Multi-die Interconnect Bridge) is Intel's proprietary advanced packaging technology that connects adjacent semiconductor dies using small silicon bridges. Rather than manufacturing one enormous monolithic chip, the approach integrates multiple compute chips and HBM stacks into a single package, with the aim of building larger semiconductor systems.
The configurations reported by ZDNet Korea fall into three stages.
| Stage | Package size | HBM stacks | EMIB bridges |
|---|---|---|---|
| Example commercialized in 2026 | Up to 120×120mm | 12 | 20 or more |
| Example in development | Targeting 120×180mm or larger | 16 or more | 38 or more |
| Future concept (timing not disclosed) | 240×240mm | 32 or more | 70 or more |
These examples were not announced as the specifications of any particular AI accelerator, and no product names have been given for each stage. The HBM count also refers to the number of memory stacks on the package, not memory capacity or bandwidth directly. Those depend on the HBM generation, stacking configuration and other factors, so product performance cannot be judged from the stack count alone.
Meanwhile, Figure 9 on page 5 of Intel's published technical brief shows a 2026 configuration of roughly 120×120mm with 12 HBM stacks and more than 20 EMIBs. The 2028 roadmap expands this to a package larger than 120×180mm with more than 24 HBM stacks and more than 38 EMIBs. The reported explanation of "16 or more HBM stacks in the in-development configuration" does not necessarily match the "more than 24 HBM stacks in 2028" plan in the official document, as they may refer to different configurations. It is therefore not possible to combine these sources and conclude that a 240mm package with 70 or more EMIBs will reach mass production in 2028.
Package Area Quadruples, and EMIB Demand Is Expected to Rise
Scaling a package from 120×120mm to 240×240mm quadruples its area as calculated from its outer dimensions: 14,400mm² for the current configuration versus 57,600mm² in the future concept. This compares the package footprint only and does not mean compute performance or memory bandwidth would quadruple.
The EMIB count also rises, from 20 or more in the 2026 example to 70 or more in the future concept. Because both figures are lower bounds, dividing 70 by 20 to get 3.5x cannot be treated as the growth rate in EMIB demand. Estimating actual demand would require knowing not only the number of bridges per product but also how many units of each product will ship.
Still, the direction Intel is pursuing is clear. As more compute chips and HBM stacks go into AI chip packages, more EMIBs are needed to connect them. The shift to larger packages could widen opportunities for Intel's advanced packaging technology, though a higher component count per product should be distinguished from higher production volume of finished products.
EMIB's Strength: 90% Wafer Utilization; EMIB-T Improves Power Delivery
Intel's technical brief states that EMIB bridges achieve 90% wafer utilization, compared with 60% for a silicon/redistribution-layer interposer at 8x reticle scale. A reticle is the master pattern used to expose circuits onto a wafer, and the multiplier here indicates the scale of the comparison technology. Wafer utilization measures how efficiently material is used and is distinct from the yield of finished semiconductor packages.
EMIB's defining feature is that small silicon bridges are placed only where high-density die-to-die connections are needed. Unlike approaches that lay a large silicon interposer beneath multiple dies, it embeds the localized connections in an organic substrate. According to Intel, this lets it skip large interposers and the associated wafer-level stacking steps, improving silicon utilization.
However, 90% wafer utilization does not mean 90% of manufactured EMIBs are good. Defects can arise not only from the bridge's own electrical quality but also in later steps such as embedding it in the substrate and mounting dies. Likewise, the gap between 90% and 60% utilization cannot be converted directly into a manufacturing cost reduction.
Intel is also developing "EMIB-T," an evolution of EMIB. In addition to the conventional horizontal high-density wiring, EMIB-T includes through-silicon vias (TSVs) running vertically through the silicon bridge. This secures a path for delivering power from the substrate to the chips as well as die-to-die signal connections.
Intel says this power delivery structure suppresses DC and AC power noise and can support high-speed communication for high-bandwidth memory such as HBM4 and for the UCIe chiplet interconnect standard. Lee also told ZDNet Korea that EMIB-T can place high-density silicon wiring only where needed, allowing flexible scaling to larger chips. Larger packages require not just area for compute chips and HBM, but also technology to connect them at high speed and supply stable power.
Substrate Shortages Limit Output, and Mass Production Will Need Stronger Inspection
As Intel seeks wider EMIB adoption, a shortage of advanced organic substrates is already constraining production. In Intel's prepared remarks for its Q3 2026 earnings, released October 29, CEO Lip-Bu Tan said Intel is increasing Intel 3 wafer output, but an industry-wide substrate shortage is hindering higher EMIB product volumes. That comment concerned supply of existing server products and did not disclose manufacturing issues or defect rates for the 240mm future concept.
Although EMIB avoids the use of large interposers, the organic substrate on which bridges and dies are mounted is still required. Even if silicon is used efficiently, shipments of finished products are hard to increase if substrate supply cannot keep up. High wafer utilization and a substrate shortage can both be issues at once because they reflect different parts of the manufacturing process.
In the same earnings materials, Intel also said talks with external customers on EMIB and EMIB-T are progressing. It added that it is expanding advanced packaging capacity in New Mexico in the U.S. and in Malaysia ahead of customer production ramps planned for 2027. However, it did not say this investment corresponds directly to the future concept with 70 or more EMIBs, and it does not indicate a mass production date for 240mm packages.
Furthermore, the larger and more complex a package becomes, the more important post-manufacturing inspection is. Intel's technical brief says that, in addition to selecting and mounting verified good dies, testing the completed system as a whole is essential to managing quality and cost. When dozens of EMIBs are combined with many compute chips and HBM stacks, it is necessary to confirm not only that each component works but that the whole system operates correctly after assembly, including connections and power delivery.
Intel's concept of more than 70 EMIBs symbolizes the evolution of advanced packaging to handle ever-larger AI chips. EMIB, which uses localized silicon bridges, offers a way to connect many compute chips and HBM stacks at high density without relying on a huge interposer. Whether it leads to actual products, however, depends on specifying target products and production schedules, as well as securing advanced substrates and building inspection capability for assembled packages. Going forward, attention will be on whether a specific product using a 240mm package is announced, and whether Intel can secure the supply capacity needed for mass production at the advanced packaging sites it is expanding.