TrendForce News reported on September 23 that the yield rate for Intel's EMIB packaging substrates has improved from roughly 30% in Q2 2026 to approximately 45% currently. The figures originate from anonymous industry sources, who reportedly indicate the supply chain is targeting a yield of 60% by Q1 2027.
Intel is working to expand its next-generation "EMIB-T" technology for use in AI semiconductors. However, an improvement in the rate at which substrates can be manufactured as good units doesn't mean finished products—incorporating chips and high-bandwidth memory (HBM)—can be shipped at the same rate.
The newly reported figures offer clues about which processes are advancing toward mass production and where uncertainty still remains.
How Much Has Substrate Yield Actually Improved?
The yield figures reported by TrendForce News pertain specifically to EMIB substrates, not Intel's finished packages. While reports also suggest that yields are more stable among Japanese suppliers, specific figures and comparison conditions for individual companies have not been disclosed.
According to TrendForce News, EMIB substrate yield improved from approximately 30% in Q2 2026 to approximately 45% as of September of the same year. Meanwhile, the figures of 50% for Q4 2026 and 60% for Q1 2027 represent targets set by the supply chain.
| Timeframe | Substrate Yield | Status of Figure |
|---|---|---|
| Q2 2026 | ~30% | Past estimate based on industry sources |
| September 2026 | ~45% | Current estimate based on industry sources |
| Q4 2026 | 50% | Target set by supply chain |
| Q1 2027 | 60% | Target set by supply chain |
However, there isn't enough information available to treat the first two figures as continuous data measured by the same supplier for substrates of identical specifications. Details such as the number of units processed, criteria for determining good units, and breakdowns by company have not been disclosed.
If we assume the same specification of substrate was processed in the same quantities and the criteria for judging good units remained unchanged, an improvement in yield from 30% to 45% would mean a 50% increase in the number of good units obtained. However, this simple calculation cannot be directly applied to actual supply volumes.
The target figures also warrant caution.
An executive at Taiwanese substrate maker Unimicron told CommonWealth Magazine that the company, along with two Japanese firms, is targeting a 50% yield rate during the initial mass production phase in 2027. This article, published in August following a July earnings briefing, doesn't necessarily align in terms of the companies or process conditions covered with the industry sources' "60% by Q1 2027" target reported on September 23.
Therefore, these two figures cannot be combined to conclude that "all suppliers will reach 60% by early 2027."
Embedding Small Silicon Bridges Within the Substrate
Intel's EMIB technology places small silicon bridges at the junctions where multiple chips sit adjacent to each other, embedding these bridges within the packaging substrate to connect the chips.
EMIB-T adds through-silicon vias to these bridges, creating pathways to also supply power from the substrate side to the chips.
According to Intel's explanation, this approach avoids the need for a large-area silicon interposer, allowing silicon to be placed only where high-density wiring is required. This could potentially reduce costs associated with silicon materials and wiring.
However, this doesn't indicate by what percentage the finished package will be cheaper than competing approaches.
If substrate defect rates are high, more substrates must be processed to obtain the same number of good units. As a result, manufacturing costs end up being borne by a smaller pool of good units. Even if material costs are reduced by using silicon only where necessary, if substrate manufacturing costs themselves or subsequent assembly process costs increase, this doesn't guarantee a price advantage for the finished product.
With EMIB, the substrate manufacturer incorporates silicon bridges directly into the base structure it produces.
While this allows high-density connection points to be created only where needed, it requires extremely precise alignment of bridge positioning and connection surfaces during the substrate manufacturing stage.
TrendForce News, citing an interview from CommonWealth Magazine, reports that differing thermal expansion coefficients between silicon and organic substrates are one factor making this process difficult.
The silicon bridges must remain in their designated positions even after undergoing heating processes, while also maintaining precise connection surfaces with the chips mounted above them.
The reported yield of approximately 45% indicates that defects remain common at the substrate manufacturing stage. However, it hasn't been disclosed which types of defects are the primary cause of rejection, or how much each process step contributes to the overall defect rate.
Therefore, the remaining defects cannot be attributed solely to differences in thermal expansion coefficients.
CoWoS, the comparison technology, also isn't a single unified approach.
According to TSMC's official explanation, CoWoS-S uses a large silicon interposer. CoWoS-L, on the other hand, incorporates localized silicon interconnect components into an interposer built using redistribution layers (RDL). The first version, at 3.5x reticle size, has been in mass production since 2024.
As a result, applying the simple contrast of "EMIB uses localized silicon bridges while CoWoS uses full-coverage silicon" to CoWoS-L specifically fails to accurately represent the technical structure.
One key difference lies in the division of manufacturing processes—specifically, whether high-density localized wiring is incorporated into the packaging substrate itself, or into the interposer placed on top of it.
Capacity Investment Is Advancing, But EMIB-T-Specific Supply Volume Remains Unclear
In its Q4 2025 earnings presentation materials, Intel indicated its intention to improve quality and yield for both EMIB and EMIB-T, addressing customer demand to ramp up production starting in the latter half of 2026.
While this demonstrates Intel's commitment to improving yield, it doesn't mean Intel itself has confirmed the substrate yield figures reported this time.
Additionally, while Intel states it has been mass-producing conventional EMIB since 2017, this track record cannot be directly applied to the yield rates of the newer EMIB-T substrates.
On the substrate manufacturer side, capital investment is already underway.
Ibiden announced plans to invest approximately 500 billion yen between fiscal 2026 and fiscal 2028 to expand production capacity for high-performance IC packaging substrates used in AI servers and similar applications. The company plans to enhance facilities, including existing plants, with mass production beginning in stages from fiscal 2027 onward.
However, the company's announcement materials do not specify that this entire 500 billion yen investment is directed toward EMIB-T.
Therefore, this investment figure cannot be used to reverse-calculate the monthly supply volume of EMIB-T substrates destined for Intel, or the number of finished AI semiconductor products shipped using them.
Care must also be taken regarding timing, as different benchmarks are being used.
Ibiden's stated timeframe of "from fiscal 2027" refers to a facility operation plan based on the Japanese company's fiscal year. Meanwhile, the "60% by Q1 2027" figure reported by TrendForce News refers to the target timing for substrate yield improvement.
The timing of facility startup, the timing of substrate yield improvement, and the timing of finished product shipments to customers are all separate matters. There is currently no basis for linking these three elements into a single, unified mass production schedule.
Supply volume also isn't determined by facility capacity alone.
To become a finished product that can be shipped to customers, the processing chips and HBM to be mounted on the substrate must be secured, and the assembled package must also pass post-assembly inspection.
Even in the manufacturing process outlined by Intel itself, individual chip binning, package-level testing, and final system testing exist as separate, distinct steps.
Therefore, the 45% substrate yield reported this time cannot be directly compared, under identical measurement conditions, with the higher yield figures previously reported for EMIB technology as a whole.
Customer Adoption Forecasts Are Separate From Actual Product Shipments
According to independent research published by TrendForce on September 18, Google is predicted to adopt EMIB-T in 2027, while AWS is reportedly testing EMIB technology as well.
However, neither Google nor AWS has themselves announced that they will mass-produce or ship products adopting EMIB-T within that timeframe.
The same research also predicts that, due to factors including technological maturity and yield rates, CoWoS-L will remain the dominant advanced packaging method for AI semiconductors through 2028.
Growing interest in EMIB-T is a separate matter from replacing the currently dominant mass production method within a short timeframe.
If substrate yield improves to the targeted levels, it could become easier to secure a stable supply of good-quality substrates.
The next point worth watching is the extent to which finished packages using EMIB-T substrates pass customer inspection, and how many units actually end up being shipped monthly.
If Intel and its suppliers begin disclosing performance figures for each individual process step, it will become easier to determine whether the material-level advantages of EMIB-T—placing silicon only where necessary—actually translate into improved final manufacturing costs and supply capacity.