Intel Foundry has set a new benchmark for how far a single package can scale an AI accelerator. The EMIB-T technology suite unveiled at IEEE ECTC 2026 packs compute and memory silicon equivalent to more than 9x reticle size into a package exceeding 120×120mm. In a separate test vehicle, the company also shrank die-to-die interconnect pitch down to 25µm.
What matters more than the area expansion itself is that both size and speed were pushed up simultaneously. Intel demonstrated HBM4E at over 12Gbps and UCIe chiplet-to-chiplet links at 64Gbps. EMIB-T adds through-silicon vias to a localized silicon bridge, concentrating wiring and power delivery at the chip boundary. If this proves viable at volume, the race to scale AI chips will shift from the ability to build a large interposer toward designs that connect only where needed, at high density.
What "more than 9x reticle" means
The reticle defines the exposure field used to transfer semiconductor circuits onto a wafer. A single die is normally confined to one exposure field, and any wiring plane exceeding that requires stitching to join multiple fields. To get around this, compute dies, I/O dies, and HBM are fabricated separately and then assembled into a single system on the package. While chiplets can improve the yield of individual dies, more dies and more boundaries make wiring, power delivery, and inspection progressively harder.
In its main ECTC 2026 presentation, Intel showed a combination of a 25µm first-layer interconnect, a package exceeding 120mm square, and more than 9x reticle-equivalent silicon. A finer pitch allows more connections to be packed around a limited die perimeter. However, the 25µm figure comes from a test vehicle linking two 1x-reticle dies via a single 3×18mm bridge — Intel has not disclosed that the entire 9x+ configuration was assembled using 25µm pitch throughout.
The "over 10x" figure belongs to a separate demonstration. An ECTC paper on packaging technology for ultra-large die complexes reported void-free encapsulation processes for 5x and over-10x reticle-equivalent configurations using EMIB, and over-4x reticle-equivalent configurations using Foveros. That case is an encapsulation achievement — it is not a claim that 25µm pitch, 12Gbps+ HBM4E, and 64Gbps UCIe were all demonstrated together on the same over-10x package.
TSVs shorten the power path to HBM4E
Conventional EMIB embeds a small silicon bridge into the package substrate, connecting only adjacent dies at high density. Unlike a large silicon interposer, areas without a bridge connect the die to the organic substrate through ordinary bumps. Intel has mass-produced EMIB since 2017 and used it in server and HPC products.
The "T" in EMIB-T refers to the TSVs — through-silicon vias — added to the bridge. In the conventional structure, power around the bridge has to detour laterally; EMIB-T instead delivers power through a vertical path straight through the bridge to locations near the die or HBM. As HBM pin counts and signal speeds rise, power and signal wiring compete for limited area, and this shortened path helps.
According to SemiAnalysis's analysis of Intel's ECTC materials, Intel reported that routing TSVs through the structure reduced DC voltage drop by 68–80%. MIM capacitors placed within the bridge reportedly improved the power network's AC impedance by more than 82% compared to an EMIB-T configuration without bridge capacitors. On the signal side, eye opening at 12Gbps widened to about 67% without receiver equalization, and to about 72.5% with one-tap decision feedback equalization. Both simulation and measured results indicate that 12Gbps+ HBM4E now falls within electrically achievable range.
UCIe's 64Gbps points in the same direction. UCIe 3.0, released by the UCIe Consortium in 2025, doubled the ceiling from 32GT/s to 64GT/s. Intel's demonstration shows that chiplet-to-chiplet connections over EMIB-T can reach that top rate — a common interconnect foundation for combining chiplets built with other companies' processes and IP.
The economics of local bridges versus full-area interposers
EMIB-T's economics stem from not using large silicon. Conventional 2.5D packaging such as CoWoS-S places a silicon interposer beneath the entire area of the logic die and HBM. Once the area exceeds the reticle limit, stitching multiple exposure fields together becomes necessary. Every time the package grows, the interposer must occupy the same expanded area.
EMIB-T instead places small bridges only at the die boundaries that require high-density connections. By Intel's estimate, bridge wafer utilization runs at around 90%. In contrast, a full-area interposer for an over-8x reticle-equivalent configuration must cut a huge rectangle from a circular wafer, which can push utilization down to around 60%. The difference in raw material usage is substantial. That said, this is Intel's own comparison — it does not account for differences in finished-package yield or equipment depreciation costs.
The manufacturing flow also differs. Small bridges are fabricated on a wafer, embedded into a large rectangular organic substrate panel, and then diced individually — meaning the overall package is less constrained by circular wafer dimensions. Additionally, different bridges can be chosen for different connection types — logic-to-logic, logic-to-HBM, and so on. Area savings combined with flexibility in placing heterogeneous dies are the differentiators Intel is emphasizing.
Beyond 25µm, the yield wall gets thicker
As packages grow larger, problems beyond the bridge itself start to dominate. The distance underfill resin must flow increases, making voids more likely to remain. Differential thermal expansion after assembly warps the substrate, causing bump misalignment and connection failures. The ECTC paper on ultra-large packages also cited the need to jointly address power noise, yield assurance through redundant design, thermal management, and warpage.
Below 25µm, solder volume drops sharply. Drawing on Intel's test results, SemiAnalysis assesses that assembly yield, bump formation, and equipment placement accuracy — rather than wiring density within the bridge — become the binding constraints. Shrinking the pitch can increase connection count, but if shorts and opens increase along with it, the result isn't a viable product.
For research purposes, Intel also displayed a 240×240mm quarter-panel test vehicle. However, SemiAnalysis reported on-site that this prototype exhibited significant warpage. At this scale, substrate transport, alignment of multilayer wiring, and panel-wide patterning all run into trouble. There remains a considerable gap in process development between the 120mm-square roadmap and the 240mm-square research vehicle.
2028: Intel's over-12x meets TSMC's 14x
Intel has laid out plans to support roughly 6,800mm² — over 8x reticle-equivalent — in 2026, expanding to roughly 10,000mm² — over 12x — by 2028. The 2028 configuration is expected to feature 16 or more stacked HBM4/HBM5 layers and 30 or more EMIB-T bridges. According to Intel's fiscal 2025 Form 10-K, EMIB-T was introduced in 2025, with adoption expanding from 2026.
Meanwhile, as of April 2026, TSMC is already producing 5.5x-reticle CoWoS in volume. By 2028, it plans to mass-produce 14x-reticle CoWoS capable of integrating roughly 10 large compute dies with 20 stacks of HBM, advancing to over 14x by 2029. On the largest-area roadmap, TSMC leads. EMIB-T's competitive edge, then, doesn't lie in setting size records but in the material utilization efficiency of localized bridges and the flexibility to mix and match dies built on different processes.
What ECTC 2026 demonstrated is the electrical feasibility of pursuing more than 9x reticle silicon area and HBM4E-class signal speed within the same technology framework using EMIB-T. Public information does not yet include the name, yield, or cost of a mass-produced product combining this scale and speed. Once customer adoption becomes concrete and warpage and encapsulation challenges are resolved with volume-production data, the localized-bridge approach will become a primary option for AI chips.