In the first half of 2026, Intel brought its hybrid bonding technology, Foveros Direct 3D, into volume production with the Xeon 6+ "Clearwater Forest." Its bond pitch is 9µm, one generation behind the 6µm that TSMC has offered in SoIC since 2025, and TSMC has also laid out a roadmap to 4.5µm in 2029. But if you line up the pitches of volume-shipping products whose names are publicly known, both companies sit at 9µm. The vertical gap is a difference in what each company can offer, not yet a difference in what each is actually shipping. This article looks at that gap through two points: a product-level comparison at matched pitch, and the fact that Intel has not attached a volume-production year to its next-generation 3µm node.
The 9µm Intel put into volume in early 2026, and the 6µm TSMC has offered since 2025
The Xeon 6+ "Clearwater Forest" is the first product on Intel 18A to apply Foveros Direct 3D in volume. It connects the compute tiles and I/O tiles directly to an active base tile through copper-to-copper bonds at a 9µm pitch. Intel Foundry explains that this bonding required 18A-PT, a dedicated variant of Intel 18A.
Intel Foundry's official technology page describes the generations of Foveros Direct 3D this way: the first generation uses copper bonds at a 9µm pitch, and the second shrinks to 3µm. The smaller the pitch, the more connections can run along each edge of a die.
At its 2026 North American Technology Symposium, TSMC presented a roadmap for SoIC bond pitch. It goes from 9µm in 2023 to 6µm in 2025, with a plan to shrink to 4.5µm in 2029.
Looking at the vertical numbers alone, TSMC was already a step ahead in 2025 of the pitch Intel took into volume production in 2026. There is a gap in the horizontal direction too. According to Intel Foundry's technology page, EMIB shrank its bump pitch from 55µm to 45µm in its second generation. The vertical direction (hybrid bonding) and the horizontal direction (EMIB) are separate axes, so we start by digging into the vertical pitch.
The cost and yield debate over EMIB-T versus CoWoS has already been widely aired. Here we focus on the vertical numbers, the bond pitch.
Separate the pitch on offer from the pitch in shipment, and both companies tie at 9µm
What we line up here is only the pitch of volume-shipping products whose names have been made public. That is a different axis from the pitch that can be offered in a catalog. We compare in the same unit (µm, the distance between the centers of adjacent pads), at the same point in time (2026), and within the same population: logic products currently shipping in volume that use hybrid bonding.
AMD's MI300 uses 9µm, the first generation of TSMC's SoIC. SemiAnalysis reported that the move to the 6µm second generation was put off because of technology maturity. Intel, for its part, uses the same 9µm first-generation Foveros Direct 3D in the Xeon 6+. Among volume-shipping products whose names can be confirmed from public information, the hybrid bonding pitch is the same 9µm for both AMD's MI300 and Intel's Xeon 6+.
Tom's Hardware points to the same picture. Its summary is that hybrid bonding capability has outrun adoption: TSMC offers 6µm, but the latest disclosed customers ship at 9µm. As far as public information can confirm, no product name can be found shipping in volume on the 6µm generation. That does not prove that no product uses 6µm. It is a comparison within what we could confirm.
Why does the pitch number translate directly into a technology generation? Solder microbumps need dimensions that assume they will be crushed during bonding. They have historically been scaled down from around 40µm, but even in the latest memory applications, around 10µm is close to the limit. Hybrid bonding is a technology that begins where microbumps hit that limit. Because polished, flat copper pads and the surrounding insulating film are joined directly with heat and pressure, there is no need to allow room for a bump to be crushed, and the leading edge has now been tightened to 6µm. The smaller the pitch, the more connections can run along each edge of a die, and stacked dies behave less like separate components and more like parts of the same chip.
This comparison needs caveats. Intel's 9µm is the value stated on Intel's official page, but AMD's 9µm comes from third-party analysis, so the strength of the evidence is not the same. The reason AMD did not move to 6µm is also not AMD's own explanation; it is only SemiAnalysis's analysis.
TSMC's SoIC customers also include, besides AMD, the Fujitsu Monaka CPU developed with Broadcom. TSMC is building out Chiayi AP7 in Chiayi, Taiwan, as one of its largest advanced packaging sites, with operations targeted to begin in 2026.
The vertical 3µm has no year attached, while horizontal EMIB-T has both 2027 and dimensions
Checking Intel Foundry's official pages, the volume-production years given differ from technology to technology. The packaging overview page says EMIB has been in volume production since 2017 and Foveros-S (2.5D using a silicon interposer) with an active base die since 2019, and that Foveros-R will be ready for volume production in 2027. But neither that page nor the data center technology page gives a volume-production year in its Foveros Direct 3D entry. The shrink to 3µm in the second generation is also described only as a future step, with no indication of when it will enter volume production.
Intel has announced a 3µm bond pitch for the second generation of Foveros Direct 3D without giving a volume-production year, while TSMC attaches the year 2029 to 4.5µm. The missing year stands out precisely because it is written for other technologies.
That said, the absence of a stated year does not mean no plan exists. It remains possible that Intel has given a year in academic presentations or investor materials. The data center technology page we consulted is also a document that describes Clearwater Forest as launching "in 2025," so there is a caveat about how far its content reflects the latest roadmap.
Horizontal EMIB-T comes with both a year and dimensions. In its ECTC 2025 paper, Intel demonstrated a 45µm pitch, and described 35µm as coming soon and 25µm as under development. The corresponding package spans 120×180mm, with more than 38 bridges and more than 12 reticles of dies, and supports both organic and glass-core substrates. Separately, at ECTC 2026, Intel claimed packaging cost savings of more than 40% versus CoWoS by removing the large interposer, and 12Gb/s with HBM4e. Both are Intel's own announcements, and they do not mix separate disclosures from the two different conferences, 2025 and 2026.
At the Q2 FY2026 earnings call on July 23, 2026, Intel CEO Lip-Bu Tan said of EMIB-T: "Customer interest remains very high, because it is a technology that can deliver capabilities for advanced AI silicon that today's mainstream options cannot." On the call, the company explained that it is focused on the transition to high volume and high quality to support the 2027 customer ramp, and that its backlog is growing.
The design also helps explain why EMIB-T can state this timeline. By running through-silicon vias (TSVs) through the bridge, it can secure a direct, low-resistance power delivery path from the bottom of the package. Intel Fellow Rahul Manepalli explains that this path helps with the integration of HBM4 and the next-generation HBM4e.
The rebuttal that offered pitch is an advantage, and two conditions that would break this reading
There is a strong rebuttal to this reading: that being a generation ahead in the pitch you can offer is itself an advantage when it comes to winning orders. TSMC is expanding SoIC production capacity, and TrendForce estimates that it has been roughly doubling almost every year from a base of several thousand wafers per month in 2024.
Some also point to execution risk on Intel's side. Analyst Ben Pouladian (BEP Research) judges Intel's advanced packaging as "a story for 2027 and beyond, with large execution risk. It is not a near-term factor." Research firm TrendForce reported that yield for EMIB substrates improved from about 30% in Q2 2026 to about 45% as of September, and that the supply chain is said to be targeting 50% in Q4 2026 and 60% in Q1 2027.
Intel, for its part, explained at the Q2 earnings call on July 23, 2026 that overall EMIB-T yield and reliability have met targets. But the two sides are not looking at the same thing. Intel's explanation concerns the yield and reliability of EMIB-T as a whole, while the roughly 45% TrendForce reported is for a single step, the EMIB substrate, and is a figure based on industry-source estimates. It is not a conflict in which one side must be wrong; the scope and the confidence level differ.
This reading holds only within the range of comparing volume-shipping products whose names can be confirmed from public information as of October 2026. It does not deny Intel's future ability to win orders. There are two conditions under which it would break.
The first is the point at which a product name shipping in volume at a bond pitch below 9µm can be confirmed from public information. If a product using 6µm on the TSMC side comes to light, or Intel announces a product adopting the 3µm generation, the vertical assessment would change. The second is the point at which Intel announces a volume-production year for the second-generation Foveros Direct 3D (3µm). Whether that year falls before or after TSMC's 2029 is when the vertical ranking will first settle into numbers. Tom's Hardware itself names, as the next thing to watch, whether major logic products go below 9µm in volume production.
Which condition is met first will decide the vertical assessment. Horizontally, Intel can show a 2027 timeline and a 45µm dimension, whereas its next vertical generation still lacks that kind of timeline. The place to check whether that difference disappears is the next product announcement itself.