On September 7, 2026, Intel Foundry announced that the number of 300mm wafers processed cumulatively on ASML's High-NA EUV lithography systems had surpassed 1 million. The total includes some products and layers of Core Ultra Series 3 (codenamed Panther Lake), manufactured on Intel 18A. The following day, ASML and TSMC unveiled a joint initiative for 12-inch photomasks, setting targets of a pilot line in 2031 and a compatible exposure system by 2033.
The two announcements may look like separate stories, but they actually represent the first and second halves of the same mass-production transition. Intel's 1 million wafers show that accumulated learning in handling High-NA EUV on the factory floor has reached a certain scale. TSMC's participation, meanwhile, reflects an industry-wide move to resolve the half-field exposure constraint of current 6-inch masks by shifting to a new standard together.
The figure of 1 million wafers does not represent chip production volume. Intel's disclosed cumulative total includes equipment installation and qualification testing, R&D, and mass production all combined. It does not mean 1 million wafers' worth of finished Panther Lake chips exist, nor can one conclude that Intel now has greater monthly production capacity than its rivals. Even so, this number carries a weight distinct from a production count.
What the 1 million wafers represent, and the process learning Intel gained
According to Intel, some layers of Panther Lake processed using High-NA EUV meet or exceed the performance of equivalent layers processed using conventional 0.33 NA EUV NXE systems. Overlay accuracy, throughput, and uptime are also said to align with Intel's expectations. Rather than making High-NA a dedicated process used exclusively on its own, Intel designed the same layers to be processable on either NXE or High-NA systems, preserving a fallback option during the mass-production ramp.
However, Intel has not disclosed actual figures for three key metrics: how many of the 1 million wafers were mass-production wafers, how many tools were used and over how many months, and what the recent monthly throughput has been. As such, 1 million wafers is not a yardstick for monthly capacity or shipment volume. It is the cumulative total of running the same fleet of tools repeatedly—from installation through research, process qualification, and actual products—while refining exposure conditions and alignment, and accumulating inspection and maintenance data.
Read this way, the figure connects to Intel's earlier track record. The company was the first to order a development-use TWINSCAN EXE:5000 in 2018, and the first to order a production-ready TWINSCAN EXE:5200 in 2022. Securing the equipment early alone does not raise yield. Time is needed to run actual product designs through the tools and feed failures back into process conditions and design rules. The head-start advantage that 1 million wafers signals lies in this number of iterations.
The processing, design, and alignment burden created by half-field exposure
High-NA EUV keeps the light wavelength at 13.5nm while raising the numerical aperture of the projection optics from the conventional 0.33 to 0.55. ASML's TWINSCAN EXE:5200B offers 8nm resolution and 40% higher image contrast than NXE systems. ASML states that the tool is capable of drawing patterns 1.7 times finer in a single exposure, enabling 2.9 times higher transistor density. This is a statement of equipment capability, not a claim that Panther Lake itself has achieved 2.9 times higher density.
To boost resolving power, High-NA's optics reduce the mask image at different magnifications horizontally and vertically. When using the current 6-inch-square mask, the area that can be handled on the wafer in a single exposure shrinks to about 26×16.5mm—half the maximum 26×33mm area of conventional EUV. Small dies can fit within a half-field, but larger dies such as AI accelerators or large-scale CPUs require stitched exposure, where left and right halves are exposed separately and their boundaries aligned.
Beyond the increased number of exposures, this also imposes burdens on design and manufacturing. Designers must decide how far to keep functional blocks from the boundary, and EDA tools must handle wiring that crosses between the two exposure fields. On the manufacturing side, circuit layers must be aligned at nanometer precision even across the boundary, and it must be confirmed that defects do not increase. This is why Intel is preparing both designs that fit within a half-field and PDKs that include stitching capability for customers.
Even though High-NA can reduce multiple exposures to a single pass, scanning the same area twice for large dies means the tool's throughput cannot be fully exploited. What determines the economics of an expensive lithography system is resolution combined with good-die throughput per hour. The advantage of entering mass production quickly using the current mask, and the time, design, and yield burdens that stitching introduces, are two sides of the same coin.
12-inch compatibility targeted for 2033, with early High-NA production proceeding on 6-inch masks
The 6×12-inch mask is a concept that doubles the current mask in one direction, enabling the entire 26×33mm field to be exposed in a single pass. ASML and TSMC have stated that their goals are to increase throughput, lower chip manufacturing costs, and eliminate the constraints imposed by stitching. But the transition will not be completed simply by enlarging the mask.
| Timing | Announced Milestone | Certainty |
|---|---|---|
| September 2026 | Intel surpasses 1 million wafers; ASML and TSMC announce 12-inch mask initiative | Achieved / Launched |
| 2030 | TSMC intends to begin using High-NA EUV for leading-edge node mass production | Planned |
| 2031 | Target of establishing a pilot line for 12-inch masks | Target |
| 2033 | Target of deploying a 12-inch-compatible High-NA exposure system for leading-edge node mass production | Target |
If the announced roadmap proceeds in this order, TSMC will begin using High-NA EUV in mass production before the 12-inch pilot line is established. This suggests that in the initial adoption phase around 2030, TSMC—like Intel—will likely rely on the current 6-inch mask and use stitching for the layers that require it. The 12-inch mask is not a prerequisite for adopting High-NA. Rather, this is a two-stage approach: first ramp into mass production using the existing standard, then move to the larger mask once the number of layers using the technology grows and the throughput penalty becomes significant.
Moreover, changing the mask standard affects blanks, the tools that write circuit patterns, and defect inspection and repair equipment. Cleaning equipment, protective pellicles, and in-fab transport systems must all be adapted to the new dimensions as well. The mask stage on the exposure tool itself must also be redesigned. The reason Intel has spent more than three years seeking cooperation from ASML and mask makers, and drawing in EDA and materials companies, is that this cannot be achieved through a single company's factory investment alone. The long lead time spanning 2031 to 2033 reflects the breadth of the supply chain involved more than any slowness in the technology itself.
TSMC's participation broadens industry cooperation on larger masks
With TSMC joining the large-mask initiative, Intel's proposal has advanced toward becoming a leading industry standard candidate. Suppliers of masks and inspection equipment find it easier to recoup development costs once they know multiple major customers will adopt the same dimensions. ASML, too, gains better visibility into demand for compatible tools. As standardization progresses, the risk of Intel alone bearing the cost decreases, and the range of available materials and equipment options expands.
At the same time, as the standard spreads, the 12-inch format itself ceases to be a differentiator unique to Intel. Even so, Intel's early learning does not disappear. Intel has already run mass-production layers on the current mask and holds data on stitching design rules and PDKs, overlay control, and equipment maintenance. TSMC has signaled intent to bring High-NA into mass production starting in 2030, but has not yet disclosed which layers or how many tools will be involved. The gap between the two companies should be measured not by who owns the equipment, but by who can stabilize yield and throughput simultaneously, and how quickly.
This also carries a separate significance for Intel. Panther Lake on 18A serves as a proving ground for learning the process using Intel's own products, but what Intel Foundry's customers want is a manufacturing service that can reproduce the same results with their own designs. Unless the experience from those 1 million wafers is translated into PDKs and design constraints that customers can use, along with clear cost and lead-time figures, Intel's early adoption will not directly translate into foundry orders.
Production breakdown and real-world performance figures to watch next
Intel's 1 million wafers serve as evidence that High-NA EUV has moved beyond being a purely research-stage tool. However, judging its strength as a mass-production technology requires knowing the share of wafers that were actual production runs, the number of layers used for Panther Lake, yield rates when stitching is used, and real-world throughput. Whether the three metrics Intel described as meeting expectations will eventually be backed by actual numbers is the next thing to watch.
On the large-mask side, it will be important to see who operates the 2031 pilot line and which mask blank, pattern-writing, and inspection companies participate. It has also not been disclosed whether existing EXE:5000 and EXE:5200B systems can be retrofitted for 12-inch compatibility, or whether entirely new tools will be required. This condition will heavily influence both investment costs and the pace of the transition.
Competition in High-NA EUV has moved beyond the stage of simply installing the first tools, into a phase where mass production runs on current masks while the next standard is cultivated in parallel. Intel's 1 million wafers and TSMC's participation illustrate this shift from both sides. The key questions ahead are how far productivity can be pushed on 6-inch masks by 2030, and whether the 2031 pilot line can be successfully linked to a 2033 production-ready system. As the transition to larger masks progresses, it should become possible to preserve High-NA's resolving power while reducing the stitching burden that arises with large dies.