Intel has published product documentation for "Starfire," an SoC aimed at use in spacecraft. It uses Intel 18A for the CPU cores and NPU, and Intel 3 for the GPU, combined into a single package via Foveros. Beyond the headline figure of up to 75 TOPS, its defining feature is a heterogeneous compute configuration that integrates CPU, GPU, and NPU.
However, there is no fact yet that Starfire has flown in orbit. The document, dated July 9, 2026, states that sample availability is planned for Q3 of that year, and explicitly notes that radiation characteristics are "under evaluation." What's new here isn't a flight track record, but rather Intel's attempt to bring its advanced process—already in volume production domestically in the US—and its heterogeneous chiplet design, also deployed in PC products, into the government and space market.
Combining 18A and Intel 3 into a single Foveros package
Starfire comes in low-power and high-performance variants, both equipped with 4 P-cores and 4 LPE-cores. In the low-power variant, the P-cores run at 1.0GHz and the LPE-cores at 850MHz, with the GPU running from 800MHz to 1.0GHz. The high-performance variant raises these to 3.1GHz, 2.1GHz, and 2.0GHz respectively.
| Spec | Low-Power Variant | High-Performance Variant |
|---|---|---|
| CPU | 4 P-cores + 4 LPE-cores | 4 P-cores + 4 LPE-cores |
| NPU | 3 tiles, Intel 18A | 3 tiles, Intel 18A |
| GPU | 4 Xe cores / 64 EU, Intel 3 | 4 Xe cores / 64 EU, Intel 3 |
| AI Performance | Up to 45 TOPS | Up to 75 TOPS |
| TDP | 10W | 35W |
Common specifications include 12 lanes of PCIe 4.0, LPDDR5 or DDR5 memory, a junction temperature range of minus 55°C to 125°C, and a designed-for lifetime of 10+ years. What the document presents is "Lifetime," not a warranty period—it cannot be read as a guarantee of 10+ years of fault-free operation. Likewise, the temperature figure refers not to ambient temperature but to the junction temperature range inside the chip.
Foveros's role is to combine compute blocks manufactured on different processes. Intel 18A adopts RibbonFET and the backside power delivery technology PowerVia, and is being mass-produced domestically in the US. Intel has also deployed multi-chiplet configurations using 18A and Foveros in the PC-oriented Core Ultra Series 3. Starfire represents a proposal to bring this same heterogeneous integration philosophy into the space domain, though Intel has not described it as a Panther Lake derivative.
75 TOPS alone doesn't determine space applications
Starfire's headline figure of up to 75 TOPS is eye-catching. But the document contains no mention of compute precision, nor does it specify how many TOPS are handled by the CPU, GPU, and NPU respectively. The same chip can yield different figures depending on precision. Platform-wide TOPS totals combining multiple compute units cannot be directly compared with figures for standalone accelerators.
The work performed by onboard AI in spacecraft differs from that of ground-based data centers. NASA cites use cases for its next-generation High Performance Spaceflight Computing (HPSC) that include analyzing sensor data onboard and enabling autonomous decision-making even in locations with significant communication delays. Under constrained power and communication bandwidth, what really determines effective performance is how consistently the system can sustain tasks such as filtering observation imagery or making navigation decisions.
For comparison, Microchip's PIC64-HPSC publishes figures of 8 RISC-V X280 cores and up to 2 TOPS of INT8 vector compute. On paper, Starfire's numbers look larger, but because the compute precisions differ, this doesn't demonstrate a real performance gap. However, PIC64-HPSC's product documentation includes dual-core lockstep and fault monitoring. It also features SpaceWire and 240Gbps TSN Ethernet, plus security functions including post-quantum cryptography. Starfire's single-page documentation, by contrast, only specifies PCIe and memory connectivity—spacecraft-specific interfaces, fault-containment mechanisms, and the software environment remain unknown.
75 TOPS alone cannot determine whether a chip should be adopted. What precision and power consumption can it sustain performance at? Can it maintain performance while detecting and correcting radiation-induced bit flips? These are the factors that actually determine adoption decisions.
The "under evaluation" note in the radiation section determines the product's stage
The single line in Intel's documentation that deserves the most attention is the note in the radiation section: "TID, SEL, SEE under evaluation." TID (Total Ionizing Dose) is the cumulative amount of ionizing radiation absorbed over time, which causes threshold voltage shifts and increased leakage current. SEE (Single Event Effects) is a general term for effects caused by a single high-energy particle passing through. Some result merely in bit flips, while others—via SEL (Single Event Latchup)—cause excessive current flow that can damage the circuit.
For space-grade components, temperature range and lifetime figures alone cannot be used to assess this risk. For example, the PIC64-HPSC1000-RH publishes, alongside the same minus 55°C to 125°C temperature range as Starfire, a maximum TID of 200krad(Si) and SEL immunity up to 78MeV·cm²/mg. These figures serve as material for determining usable orbits, shielding requirements, and mission duration.
For Starfire, there is still no data on TID tolerance, the linear energy transfer threshold below which SEL does not occur, SEE cross-section, or the particles and operating conditions used in testing. It's also unclear whether radiation hardness is built into the process itself, compensated for through design-level redundancy, or predicated on system-level shielding. "Space grade survivability" represents a product goal, but at this stage does not imply completed spaceflight qualification.
NASA's HPSC is also continuing radiation, thermal, shock, and functional testing through 2026. NASA has stated that following the current round of testing, it plans to obtain spaceflight qualification and incorporate the chip into future lunar, planetary, and crewed exploration missions. Between an initial sample working and withstanding a long-duration spaceflight lie test results and design reviews. Starfire cannot skip this same sequence either.
A domestically-manufactured proposal for government customers—test data comes next
Starfire's documentation bolds "competitive pricing" and "domestic US manufacturing" side by side, along with contact information for Intel Government Technologies. With no price list or order numbers, at this stage it reads more as a proposal document aimed at finding government and defense-industry customers. In separate government-facing documentation, Intel has described bringing defense-industry companies such as Boeing and Northrop Grumman into Intel 18A's prototyping environment through RAMP-C. The ability to trace advanced logic from design through mass production domestically within the US is arguably a more concrete procurement advantage than the pricing Starfire touts.
That said, domestic manufacturing is no substitute for space reliability. What needs to be confirmed with Q3 2026 samples are figures showing pass/fail results for TID and SEL, SEE occurrence rates, and lot-to-lot variation. Fault detection and recovery mechanisms are also essential. On the AI performance side, a breakdown of the 45 TOPS and 75 TOPS figures, compute precision, and sustained temperature and power consumption will be needed. Once the target orbit and intended mission become clear, the market Starfire is aiming for can be narrowed down. The release of evaluation boards, an OS, and a development environment will be the condition for customers to begin prototyping.
The concept of bringing Intel 18A into space expands the range of options for incorporating onboard AI and chiplet designs into spacecraft. Starfire can only be properly evaluated as a product not through the next round of promotional material, but once the conditions and results of radiation testing are made public.