Instantly retrieving a stored, complete image from a cue that is partially missing or buried in noise—this associative memory function, which the human brain performs routinely, has been a target for reproduction in semiconductor circuits for nearly half a century, a pursuit that has continually run up against physical limitations. Memristor (resistive-switching memory, RRAM) crossbar arrays, which have drawn attention as brain-inspired circuits, can compute matrix-vector products in a single step by directly exploiting Ohm's law and Kirchhoff's law. However, real analog devices exhibit extremely large manufacturing variation, and a certain fraction inevitably become defective, becoming stuck at a fixed resistance value. Conventional associative memory networks have been bound by a double constraint: even a small fraction of defective devices causes a sharp collapse in memory capacity, and the number of patterns that can be stored increases only linearly with network size.
A research team led by Professor Can Li and PhD student Chengping He of the Department of Electrical and Electronic Engineering and the Center for Advanced Semiconductor Integrated Circuits (CASIC) at the University of Hong Kong, working together with Giacomo Pedretti and Jim Ignowski of Hewlett Packard Labs (HPE), has developed a method to break through this stagnation. Rather than eliminating defects on the physical chip, the approach embeds the locations of defects directly into the learning algorithm from the outset, allowing the algorithm itself to compensate—a "hardware-adaptive learning algorithm" combined with a multilayer network architecture. The research results were published in the journal Nature Communications (2026, Volume 17, Article 3096, DOI: 10.1038/s41467-026-69958-0). The measurement data presented in the primary paper rigorously defines the concrete scope of this engineering breakthrough, which is premised on hardware imperfection.
- Conventional method (pseudo-inverse rule)
- Proposed method (hardware-adaptive)
データを表で見る
| Conventional method (pseudo-inverse rule) (Number of patterns) | Proposed method (hardware-adaptive) (Number of patterns) | |
|---|---|---|
| 0% defect rate | 120 | 190 |
| 30% defect rate | 70 | 155 |
| 50% defect rate | 35 | 115 |
Even under the extreme condition where half the devices are broken and non-functional, the new method continues to retrieve more than three times as many patterns as the conventional pseudo-inverse-based baseline method. The resilience shown in this graph points to a practical new path toward fault-tolerant design for analog neuromorphic technology, which has long been plagued by chip manufacturing yield issues.
The "Linear Ceiling" That Half a Century of Convention Placed on Associative Memory Capacity
It was physicist John Hopfield's 1982 paper on the Hopfield Neural Network (HNN) that laid the groundwork for associative memory in computer science. A fully connected population of neural elements updates its state to minimize an energy function, settling into pre-embedded memory "valleys." Even when input is partially missing or contains random noise, the system autonomously converges to the original memory state.
However, the classical single-layer Hopfield network was subject to a mathematically rigorous limit. Given a network of $N$ neurons, the number of independent patterns that can be stably stored (the memory capacity) was confined within a linear framework proportional to $N$. Under the most primitive Hebbian rule (correlation learning), the theoretical capacity limit is only about $0.136N$. As more patterns are memorized, the valleys of the energy function begin to interfere with one another, trapping the system in unintended false memories known as spurious states. Avoiding this confusion required expanding the neuron count—and thus the circuit scale—in step with any increase in memory capacity.
Furthermore, the classical single-layer Hopfield network relied on a sign function () that binarizes each neuron's state to either $+1$ or $-1$. While this structure was well suited to storing binary patterns such as black-and-white bitmaps, it was fundamentally difficult to handle the continuous-valued data (such as images with gradations or audio signals) that make up the majority of real-world data. Attempts were made to accommodate continuous values by replacing the sign function with the differentiable hyperbolic tangent function (), but as long as the network remained single-layered, it could not suppress the mutual interference (crosstalk) between overlapping continuous-valued patterns, leading to a fatal problem in which effective memory capacity collapsed to just one or a few patterns.
The very criterion for evaluating capacity also demanded redefinition from a strict engineering standpoint. Prior theoretical studies often discussed capacity in terms of whether a completely clean memory pattern could be maintained as a fixed point—a "noise-free fixed point" criterion. But the real value of associative memory lies precisely in situations where the cue itself is corrupted. In this paper, the research team set an extremely strict definition of capacity: after adding external disturbance noise with a 5% bit-flip probability to the input cue, the maximum number of patterns for which the recalled output maintains a cosine similarity of 0.99 or higher with the original stored pattern was defined as the "recall capacity."
Under this rigorous criterion, the recall capacity of the Hebbian rule shrinks to $0.127N$—an even stricter standard than the classical value ($0.132N$) computed under ideal, noise-free conditions. Under this constraint, how to construct an architecture that both withstands physical device defects and breaks through the linear limit was the greatest question standing before hardware associative memory.
A Design Philosophy That Embraces Device Imperfection Within the Learning Algorithm, Rather Than Eliminating It
Analog in-memory computing using memristors uses the conductance (electrical conductivity) of tiny devices placed at the intersections (crosspoints) of crossing wires as weights. When a voltage is applied to the input side of the wiring, current is generated at each crosspoint, and these currents are summed at the terminal end of the wiring by Kirchhoff's current law. This is a physical platform that achieves extremely high energy efficiency and low latency simultaneously, without the need to shuttle data back and forth between memory and processing units as in digital processors.
But standing in the way of this ideal physical computation is device failure. Memristors, which switch resistance states by exploiting the movement of oxygen vacancies within thin-film oxides, inevitably suffer from stuck-at faults—permanent fixation at a particular conductance state—due to manufacturing process non-uniformity and repeated electrical stress. Some devices become stuck in a high-resistance state and stop conducting; others remain stuck in a low-resistance state and continue to pass large currents. In associative memory, where thousands to tens of thousands of weights must be set precisely across a fully connected network, even a stuck-fault contamination rate of just a few percent distorts the shape of the energy landscape and makes correct recall impossible.
Conventional approaches have centered on hardware-side countermeasures: pushing semiconductor manufacturing technology to its limits to physically reduce defects, or replacing defective devices with redundant backup circuits. The strategy taken by Professor Can Li's research team is the exact opposite. Professor Li describes it as a co-design approach that weaves the characteristics of an imperfect real device into the learning process itself. Rather than fighting head-on against imperfection, the idea is to have the system learn to accept real-world imperfection.
This method, named the hardware-adaptive learning algorithm, cleverly combines pre-measurement with software-based learning. The process begins with a rigorous characterization scan of the physical chip. A write pulse is applied to each device in the integrated memristor crossbar array, and its response characteristics are read out one device at a time. At this stage, any device that fails to reach a minimum conductance threshold (for example, 5 microsiemens) even after programming is recorded as having a permanent low-conductance fault (stuck-off fault) at that location. Similarly, devices that cannot be switched to a high-resistance state are detected as stuck-on faults.
| Comparison item | Conventional single-layer Hopfield network (pseudo-inverse rule) | This study's hardware-adaptive multilayer associative memory | Conditions and applicable limits |
|---|---|---|---|
| Tolerable defect rate | Recall function collapses at around 35% | Maintains operation even under 50% fixed defects | Physical measurement and simulation on a 64×64 array |
| Capacity at 50% defect rate (MNIST) | 35 patterns | 115 patterns (approx. 3.3x conventional) | With 5% added noise, strict threshold of cosine similarity ≥0.99 |
| Scaling law (binary data) | Linear with neuron count (theoretical upper bound approx. ) | Super-linear with neuron count (measured ) | Empirically observed on correlated datasets (e.g., MNIST) |
| Scaling law (continuous-valued data) | Capacity collapse due to crosstalk (effectively unusable) | Super-linear with neuron count (measured ) | Measured with the addition of a hidden layer and activation |
| Device usage efficiency (when storing MNIST) | Baseline (reference for relative comparison) | Achieved with up to 95% fewer devices (absolute values not disclosed in paper) | Relative comparison of the total number of memristors needed to maintain the same data representation |
| State-update method and processing latency | Asynchronous sequential update (requires multiple steps) | Synchronous batch update (leverages parallel crossbar multiply-accumulate) | For 64-dimensional pattern recall, 8.8x energy efficiency, 99.7% latency reduction (absolute values not disclosed in paper) |
Once the defect map is complete, the stage of optimization shifts to software on the host computer. During training via gradient descent, a fixed mask is applied to the weight parameters corresponding to devices identified as defective, forcibly binding those weight values to zero or to the physical device's fixed value. The algorithm bypasses these failed crosspoints and cooperatively adjusts the weights of the surrounding healthy devices to construct the desired energy landscape—a mechanism in which the surviving healthy devices take over and compensate for the connective strength lost by the defective ones.
There is an important boundary to note here. This entire learning process is not on-chip online learning in which the chip autonomously learns by itself. Rather, it follows a procedure in which defect locations are measured beforehand, optimization is performed on an offline computational model, and the resulting final weights are then written back to the physical crossbar array. This approach amounts to imposing a "dedicated training" individualized for each chip after manufacturing—a hardware-algorithm co-design that directly leverages chip-to-chip variation as a design parameter.
Graceful Degradation Demonstrated Under an Extreme 50% Failure Rate
The true value of the completed hardware-adaptive learning model was tested under a harsh scenario involving progressive device destruction. The standard handwritten digit dataset MNIST was used for evaluation. As noted above, recall success was judged by the strict criterion of whether an image could be reconstructed with cosine similarity of 0.99 or higher from an input containing 5% flip noise.
The pseudo-inverse rule (projection rule), an improvement on the Hebbian rule, has been widely used as the top-tier baseline in prior research. The pseudo-inverse rule can substantially raise the capacity of a single-layer network by removing cross-correlations, but it is extremely fragile against hardware defects. In the experiments, the pseudo-inverse rule's recall accuracy began to degrade sharply once the stuck-fault rate exceeded 35%, and by 50% the number of patterns that could be stored had fallen to just 35.
By contrast, the hardware-adaptive approach—optimized in advance with the physical device defect distribution built in—retained the ability to recall 115 patterns even at the extreme failure rate of 50%. Compared with the conventional baseline method, this amounts to continuing to retrieve more than three times as many patterns.
The profile of performance degradation as the failure rate rose also showed a distinctive characteristic. In conventional circuits, once defects exceed a certain threshold, the entire recall output tends to turn into noise, resulting in catastrophic failure. In this system, however, while the upper limit on the number of storable patterns gradually decreased as the defect rate rose, the cosine similarity of recalled patterns remained at the extremely high level of 0.99, as long as the recall stayed within the remaining tolerable capacity.
The research team calls this behavior "graceful degradation." Even as physical damage accumulates in the hardware, the system as a whole does not suddenly die. Only the absolute number of memories that can be handled gradually decreases, while the purity of the memories that are retrieved is guaranteed until the very end.
Quantitative support was also obtained regarding the scaling characteristics of the single-layer configuration in a clean state. According to the research team's measurements, the recall capacity of the single-layer baseline was proportional to approximately with respect to neuron count $N$, following a framework close to strict linear scaling. Although absolute capacity nearly double that of the conventional method was achieved, the experimental data reconfirmed the theoretical boundary that, as long as the network remains single-layered, the linear ceiling cannot be exceeded.
Hidden Layers Unlock Super-Linear Capacity and Continuous-Valued Pattern Compatibility
The key to physically breaking through the linear ceiling was "multilayering" the network. The research team modified the structure of the single-layer Hopfield network by introducing a multilayer architecture with a hidden layer inserted between the input and output layers.
The presence of the hidden layer projects the internal representation of input patterns into a high-dimensional space, separating out the similarity between overlapping patterns. This simultaneously opened two breakthroughs that were impossible with a single-layer configuration. First, stable recall of "continuous-valued patterns" with gradations became possible using the differentiable function without being buried in crosstalk. Second, this gave rise to "super-linear scaling," in which the number of storable patterns increases at a pace exceeding linear as the network size (neuron count $N$) expands.
In experiments using real datasets containing correlations, such as MNIST, the research team observed a phenomenon in which memory capacity grew at a striking pace relative to neuron count. When binary patterns were memorized, recall capacity increased in proportion to approximately with respect to neuron count $N$. Furthermore, in the recall of continuous-valued patterns, the scaling exponent reached .
This super-linear scaling directly translates into a reduction in the number of physical devices required to construct the circuit. According to the paper's report, the total number of memristors needed to store and recall all patterns in the MNIST dataset was achieved with up to 95% fewer devices compared with the conventional single-layer method (the specific absolute number of devices is not disclosed in the published materials). Based on this relative ratio, the number of devices needed to maintain the same data could theoretically be compressed to roughly one-twentieth, suggesting the potential to shrink the chip's footprint.
Benefits of the multilayer design are also reported for energy consumption and processing speed. According to the paper's description, in relative comparison with the single-layer implementation, the multilayer structure recorded 2.53 to 3.28 times higher energy efficiency, and recall operation speed improved by 1x to 2x (however, the absolute values and detailed measurement conditions underlying both the baseline and comparison figures are not disclosed in the published materials).
However, the term "super-linear" requires strict scientific qualification in its interpretation. This exponential expansion of capacity has not been mathematically proven to hold universally for all uncorrelated data as a universal law. It is a phenomenon empirically observed in datasets, such as MNIST, that possess specific geometric and statistical correlations between patterns. In fact, the research team itself notes in the paper that, when the neuron count is scaled up even further, changes in the correlation structure of the patterns cause the growth in capacity to slightly slow down. A cautious perspective is essential, avoiding overgeneralization and carefully assessing what statistical properties of data are needed to obtain this gain.
The Physical Power of Synchronous Updates Demonstrated on a 64×64 RRAM Crossbar Chip
What underpins the credibility of this research is that these claims are not merely the product of computer simulation, but were actually measured and verified on a fully integrated chip implemented on a silicon substrate. The verification used a 64×64 array resistive-switching memory (RRAM) crossbar circuit, a device in the lineage of memristor technology that the University of Hong Kong and Hewlett Packard Labs have jointly developed over many years.
One major challenge in analog in-memory computing is the question of what temporal order to use when updating neuron states. In conventional implementations of the Hopfield network, "asynchronous sequential update," in which neurons are updated one at a time in sequence, has often been adopted as a safety measure to prevent unexpected oscillation and instability of the state. However, asynchronous updating kills the crossbar circuit's greatest inherent advantage: performing a single batch physical computation across all crosspoints at once. As the number of devices increases, the number of update steps explodes, worsening latency and power consumption.
To overcome this constraint, the research team implemented a "synchronous batch update" scheme on the hardware that fully exploits the physical parallelism inherent in the crossbar array—an approach in which the states of all neurons are detected simultaneously, and a voltage is applied to all columns at once to determine the next state in a single batch.
This implementation of synchronous updating dramatically shortened processing latency. According to the paper's report, in relative comparison with the conventional asynchronous sequential update, overall system processing time was reduced by 99.4%, and energy efficiency improved by 2.68 to 2.76 times (however, the specific absolute values for processing time and energy consumption under both schemes are not specified in the published materials).
Even more striking figures are reported for a recall task using 64-dimensional patterns matching the physical scale of the hardware. According to the paper's abstract, compared with asynchronous updating, the energy consumption for recall was reduced by a factor of 8.8 (an 8.8x efficiency gain), and processing latency was shortened by 99.7% (again, the absolute values for energy and latency themselves are not shown in the published materials). This demonstrates the potential of a crossbar that entrusts matrix multiply-accumulate operations to the laws of physics themselves, realized through synchronous control and stable multilayer optimization.
The Future of Edge AI and Remaining Engineering Hurdles
The application horizon suggested by this achievement lies in the field of edge AI devices, which must operate autonomously on an extremely low power budget. Wearable devices that cannot always secure a power supply, environmental sensors scattered in extreme environments, and the end-point receptors of robots all require instantaneous, low-power pattern recognition while cut off from cloud communication. An associative memory circuit that instantly restores memory from imperfect sensor signals could be an extremely useful component in such applications.
However, equating this achievement with "the completion of a general-purpose brain-type computer" must be scientifically avoided. The phrase "mimicking the brain's associative memory" merely refers metaphorically to the behavior of a specific recall algorithm that restores a whole from a partial input; it does not mean the chip has acquired the flexibility or general-purpose information-processing capability of a biological brain.
Moreover, clear unresolved engineering hurdles remain on the path to practical application and widespread adoption.
First, there is the reliance on an offline learning process. This method follows a procedure in which the location and characteristics of defects, which differ from chip to chip, are scanned by external equipment, optimized on a computer, and then written back to the devices. While this approach is extremely effective at absorbing individual chip defects, questions remain about the scalability of a process that requires characterization measurement and individualized training for every single chip on a mass-production line. How to resolve the trade-off between actual footprint and manufacturing cost, or whether the chip itself can be developed into an autonomous circuit capable of detecting and adapting to its own defects on-chip, will be the next test.
Second, there are constraints from the scale of hardware demonstrated. What was physically demonstrated this time was a single module of a 64×64 array, which is too small in scale for practical image processing or large-scale database search. When multiple crossbar arrays are tiled together to achieve larger scale, how voltage drop (IR drop) due to wiring resistance (parasitic resistance) and thermal noise affect the convergence of the multilayer network remains an unverified area.
Third, there is the need for independent third-party replication and verification of scaling on more complex real-world datasets. To what extent can the proposed architecture maintain its advantage in higher-dimensional, more feature-dispersed, real-world noisy environments beyond MNIST, where super-linear scaling was observed? There also remains the question of long-term reliability—how much the trained weights can withstand drift phenomena caused by physical device aging over time and temperature changes.
Using defective devices as they are, defects and all, and pushing back the capacity limit of physical circuits through multilayering—the significance of having this engineering approach proven on an actual chip is substantial. But before harmony between imperfect hardware and algorithms can be fully achieved, steady, incremental verification will still be needed on both the manufacturing process and circuit design fronts.