At a technical webinar held on October 21, 2026, Micron unveiled a development roadmap that brings wafer bonding and High-NA EUV lithography to next-generation DRAM. The company also disclosed plans for "vHBM," which stacks memory on top of a compute chip, and "vEIM," which is intended for AI inference on edge devices. It is aiming to begin mass production of the first generation of both products in 2028. The strategy is to advance, in parallel, the manufacturing technology that shrinks DRAM memory cells and the packaging technology that shortens the data path between memory and compute chips.
However, the "bonding" and "3D" mentioned in this announcement do not all refer to the same technology. Wafer bonding, which changes how DRAM is manufactured; 3D DRAM, which makes the memory cell itself three-dimensional; and vHBM, which places finished memory dies on top of a compute chip, each address different problems and sit at different stages of development. Separating them shows how Micron intends to extend conventional DRAM scaling and how it hopes to change the structure of memory for AI.
Skipping 4F², Micron Extends 6F² with Wafer Bonding and High-NA EUV
DRAM stores information using a basic unit consisting of a capacitor that holds charge and a transistor that controls reading and writing. The "F" in "6F²" and "4F²," which express memory cell area, refers to the minimum feature size of a given manufacturing generation. Compared at the same F, a 4F² cell is smaller than a 6F² cell and, in theory, can more easily raise memory density. But even if cell area can be reduced, a more complex manufacturing process can be a disadvantage in cost and manufacturability.
On page 16 of the technical webinar presentation, Micron states that it will not adopt the 4F² cell because of added complexity and cost, and will instead continue improving the existing 6F² cell and developing 3D DRAM. The company has researched 4F² technology for more than 20 years, but ultimately chose a different development path. This is Micron's own technology strategy, however, and does not mean the semiconductor industry as a whole has concluded that 4F² manufacturing is impossible.
The current production generation, "1γ (1-gamma)," uses EUV lithography, and the next generation, "1δ (1-delta)," is planned to ramp up in volume in the second half of 2027. 1δ aims for a bit-density improvement in the mid-20% range over 1γ, and is also expected to serve as the foundation for future HBM5, vHBM and vEIM. That density gain does not translate directly into the same rate of increase in memory product capacity or decrease in price, however. Actual product specifications and costs also depend on die size, yield, package configuration and other factors.
In later generations, Micron plans to introduce wafer bonding in "1ε (1-epsilon)," which is under development. The following generation, "ζÅ," which is in early development, will adopt High-NA EUV lithography, and "ηÅ," which is at the technology exploration stage, points toward the introduction of new materials. The company has not announced specific production years for these generations. The presentation also notes that the roadmap indicates technology development directions rather than specific timing.
High-NA EUV is not a technology that shortens the wavelength of the exposure light. According to ASML's official explanation, the EUV wavelength remains 13.5 nm, but raising the numerical aperture (NA) of the optics from 0.33 in the conventional NXE series to 0.55 in the EXE series makes it possible to form finer patterns. In other words, High-NA EUV improves the resolution of the exposure tool. Wafer bonding, on the other hand, combines circuits manufactured separately and plays a different role in advancing scaling.
How Wafer Bonding, 3D DRAM and Stacking on Compute Chips Differ
DRAM needs not only memory cells but also peripheral circuits that support reading and writing data. Examples include sense amplifiers that read the tiny charge stored in a memory cell and control circuits that select the memory region to be accessed. Even if memory cells are made smaller and denser, the area and performance of these peripheral circuits can become constraints that limit overall DRAM performance gains. How memory cells and peripheral circuits are manufactured and arranged is therefore also an important development issue.
In a technical explanation of DRAM peripheral circuits, the semiconductor research institute imec describes constraints specific to conventional manufacturing processes. When memory cells are fabricated after the peripheral circuits are formed, the peripheral circuits must withstand heat treatment at 550–600°C for several hours. This makes it difficult to apply manufacturing technology for high-performance logic semiconductors directly to DRAM peripheral circuits.
One way to ease these constraints is to manufacture the peripheral circuits and memory cells on separate wafers and bond them afterward. If the two can be made in independent processes, the peripheral circuits no longer need to withstand the high-temperature steps used to form memory cells, making it easier to choose manufacturing conditions suited to each. Although a bonding step is added, this could lead to better peripheral-circuit performance and optimized manufacturing processes. In other words, wafer bonding offers not only denser circuit placement but also the advantage of combining manufacturing processes suited to different circuits.
This is only one example of the technical thinking behind introducing wafer bonding to DRAM, however. Micron has not disclosed the specific configuration or cross-sectional structure of the circuits to be bonded in the 1ε generation, nor the effect on manufacturing cost. The method described by imec therefore cannot be treated as the specification of Micron's 1ε generation.
The main technologies presented in the announcement can be organized by what they change and their stage of development, as follows.
| Technology | What it changes and why | Development stage / production timing |
|---|---|---|
| Wafer bonding in 1ε | Changes how DRAM is manufactured and integrated. Specific bonding structure not disclosed | Under development. Production timing not disclosed |
| 3D DRAM | Makes the memory cell itself three-dimensional, raising integration density by a method different from planar scaling | 3D1 and 3D2 appear on the development roadmap. Specific timing not disclosed |
| vHBM / vEIM | Stacks memory on top of a compute chip to shorten data paths and improve efficiency | First-generation production target is 2028. Timing and performance may change |
This table classifies the technologies shown on pages 16 and 20–22 of Micron's presentation by purpose and development stage. It does not compare their performance, and the imec method used to explain wafer bonding does not represent Micron's specific product specifications. The key point is that these are technologies at different layers. Even though vHBM has a 2028 production target, that does not mean 3D DRAM, which makes the memory cell itself three-dimensional, will be mass-produced at the same time.
vHBM Stacks on the Compute Chip to Improve Data Transfer and Heat Dissipation
HBM (High Bandwidth Memory) is a technology that stacks multiple DRAM dies vertically to secure high memory bandwidth. In the typical conventional configuration, stacked HBM is placed beside a compute chip such as a GPU and connected through a wiring substrate called an interposer. Micron's "vHBM" changes this arrangement, with the concept of stacking memory on top of the compute chip. Shortening the distance between compute and memory is intended to improve data transfer efficiency.
Page 20 of the presentation shows the differences among standard HBM, custom HBM and vHBM. In custom HBM, logic functions co-designed with the customer are built into the base die that underlies the stacked memory. vHBM goes further by changing the arrangement of memory and compute, aiming to improve data transferred per unit of power and the number of tokens AI generates. The figure explains a design concept, however, and no measured performance improvement was presented.
Connecting compute and memory in close proximity also requires advances in semiconductor package assembly technology. Micron lists the miniaturization of through-silicon vias (TSVs) and microbumps, along with copper hybrid bonding, as key technologies. The direction is to narrow the spacing between connection terminals and place more contacts at high density, making chip-to-chip data transfer more efficient.
On the other hand, a structure that stacks memory on a compute chip makes heat dissipation a major challenge. Particularly when DRAM is placed near a high-performance compute chip, the effect of heat on memory operation must be considered. In its presentation, Micron showed ideas such as placing a heat-spreading structure above the physical-layer circuit (PHY) that handles signal transmission and reception, and a design that uses both sides of the chip to release heat. Alongside denser wiring enabled by bonding technology, the company plans to develop technologies that lower thermal resistance and spread out localized heat generation.
Page 21 also depicts a configuration in which conventional HBM is placed beside the compute chip while vHBM is stacked on top of it. This suggests Micron envisions combining the two rather than having vHBM entirely replace conventional HBM. The design challenge is how to balance the required capacity, data transfer bandwidth and heat dissipation while taking advantage of placing memory close to the compute chip.
First-Generation vHBM and vEIM Target 2028 Mass Production
In the product roadmap shown on page 22 of the presentation, Micron sets the production targets for both the first-generation vHBM and the first-generation vEIM at 2028. Next-generation models of both products are placed in the following years, but a footnote states that these are only target production timings and that timing and performance may change depending on development progress. Unlike the DRAM manufacturing technology roadmap, which sets no specific years, this one indicates target timing for productization.
vEIM is a memory technology intended for running AI inference on edge devices. For the first-generation product, the targets are 2 TB/s of memory bandwidth and keeping the energy needed to transfer one bit of data below 1 pJ. Memory bandwidth indicates the amount of data that can be transferred per unit of time, while transfer energy expresses the energy needed to move one bit of data. However, a value of under 1 pJ/bit does not represent the power consumption of an entire AI device, and actual power efficiency also depends on the compute chip, circuits other than memory, processing load and thermal design.
Micron says it will optimize the memory base die and PHY to match the semiconductor package structure and actual processing loads. This represents a shift toward designing not only the memory's own performance but also how it connects to the compute chip and how heat is removed. Following the volume ramp of 1δ-generation DRAM in the second half of 2027, a key question going forward is whether vHBM and vEIM, targeted for 2028, can deliver both data transfer efficiency and thermal performance. If these technologies reach practical use, they would broaden the options for efficiently feeding large volumes of data to AI compute chips.