- What happened: Nagare Labs announced Z2RAM, a new memory based on oxide semiconductors, and secured $5 million in a funding round led by Playground Global.
- Our estimate: If the planned 5x storage density over SRAM is achieved, the number of Groq 3 LPUs needed to hold the weights of a 1-trillion-parameter model could fall from 1,024 to about 205. However, this is a simple calculation that looks only at memory capacity.
- What would break the assumption: If memory tile samples, targeted within four years, fail to demonstrate the 5x density over SRAM in actual measurements, the projected chip-count reduction will not hold.
Nagare Labs, a U.S. company whose board includes former Intel CEO Pat Gelsinger, came out of stealth mode on October 26, 2026, and announced Z2RAM, a new memory that uses oxide semiconductors. It also disclosed that it has secured $5 million in a funding round led by Playground Global. The company aims to combine access speed comparable to SRAM with storage density close to DRAM, placing large-capacity memory right next to the compute circuits of AI accelerators. If the first-generation target of 5x the storage density of SRAM is achieved, the number of Groq 3 LPUs needed to store a 1-trillion-parameter model with 4-bit quantization could, by simple calculation, fall from 1,024 to about 205. However, the 5x figure is a prediction based on the company's layout simulations, not performance confirmed in an actual memory product.
The LPUs needed for a 1-trillion-parameter AI model drop from 1,024 to about 205, by this calculation
The basic structure of Z2RAM is a memory cell made of two transistors. A typical DRAM cell stores one bit using one transistor and one capacitor (a component that holds charge). Z2RAM instead uses a write transistor and a read transistor, and holds charge in the gate capacitance of the read side. Its defining feature is that it needs no separate capacitor. According to the Nagare Labs website, a shield structure sits between the two transistors to prevent the operation of neighboring cells from disturbing stored data.
Co-founder Suman Datta, a professor at the Georgia Institute of Technology, told The Register that Z2RAM matches SRAM in speed, while its data retention mechanism is closer to that of DRAM. In DRAM, reading changes the charge in the capacitor, so a rewrite operation is needed to restore the data. Z2RAM instead uses non-destructive readout, which lets it read without losing the stored charge, and the company says this reduces the latency that such operations introduce. Whether SRAM-equivalent speed can actually be achieved in a real product will need to be verified.
Another feature of Z2RAM is its manufacturing method, which stacks memory cells vertically. HBM increases capacity by stacking and bonding separately manufactured DRAM dies. Z2RAM, by contrast, aims for a structure in which oxide semiconductor memory layers are formed one after another on a single die. Datta explained that the approach is closer to 3D NAND flash, which stacks storage layers on the same die, than to HBM, which stacks multiple DRAM dies. The company says the design can use existing CMOS manufacturing processes and deep ultraviolet (DUV) lithography, forming the memory layers without extreme ultraviolet (EUV) lithography.
The company also emphasizes operating-temperature tolerance. Nagare Labs explains that when conventional DRAM is stacked on top of a compute chip, the DRAM must be kept at roughly 95°C or below, which constrains the operating conditions of the logic underneath. The oxide semiconductors used in Z2RAM, on the other hand, can have very low leakage current when the transistor is off. As a result, the company says charge can be retained for long periods even near AI accelerators that tend to run hot, and power consumption from frequent refreshing can also be reduced.
If this structure delivers the planned storage density, it could bring major changes to AI chip design. For example, AMD's 3D V-Cache bonds a 64MB SRAM tile to a CPU chiplet to increase cache capacity. If Z2RAM achieved 5x the storage density of SRAM in the same area, 320MB could be stored in the area equivalent to 64MB. Of course, this is a theoretical comparison based on the ratio of area to density, and AMD has not indicated any plan to adopt Z2RAM.
Applying this idea to AI inference accelerators that rely heavily on SRAM could make the effect even larger. According to NVIDIA's official technical explanation, the Groq 3 LPU (LP30) carries 500MB of on-chip SRAM per chip. SRAM is extremely fast but has low storage density, so holding the weights of a huge AI model requires many chips.
For example, if the weights of a 1-trillion-parameter AI model are quantized to 4 bits, the required storage is about 500GB by simple calculation. Storing them in LPUs with 500MB of SRAM alone would, in theory, take about 1,000 chips. NVIDIA's Groq 3 LPX houses 256 LPUs in one rack with 128GB of SRAM across the rack, so using four racks, or 1,024 chips, gives a total of 512GB, enough in principle to hold the model's weights. However, this considers only the capacity for weights and does not include the working space needed for actual inference.
Suppose Z2RAM achieves 5x the storage density in the same memory footprint and can replace the LPU's SRAM region. Memory capacity per chip would then rise from 500MB to 2.5GB. Dividing 1,024 by 5 gives about 205, which suggests the number of LPUs needed to store the weights of a 1-trillion-parameter model could fall substantially. Applying the same calculation to 8-bit quantization, the count falls from 2,048 to about 410. However, this estimate assumes that the chip count is inversely proportional to memory capacity, and it does not predict actual chip counts or system configurations.
In reality, AI inference needs more than space to store model weights. In addition to holding the KV cache and intermediate data, compute performance, inter-chip communication bandwidth, and memory access speed all affect system scale. Also, Z2RAM's 5x density is based on a comparison with a specific SRAM design, and the same ratio is not guaranteed if it directly replaced the existing Groq 3 LPU. The figure of about 205 is therefore a conditional estimate showing the scale of the impact that Z2RAM's density improvement could have on AI systems.
Even if Z2RAM could store 2.5GB per chip, that would be less than 1% of the 288GB of HBM4 on NVIDIA's Rubin GPU. Z2RAM does not aim to simply replace HBM, but to create a fast, relatively large-capacity memory layer right next to the compute circuits. Its value lies not only in capacity but in whether it can shorten the data transfer distance between memory and compute circuits and improve bandwidth, access latency, and power consumption.
5x the density of SRAM and 14x the speed of DRAM are still projections
What matters here is that the performance underlying the estimate has not yet been demonstrated. The Nagare Labs website lists three targets for first-generation Z2RAM: "14x the speed of DRAM," "5x the storage density of SRAM," and "about one-third the read energy of SRAM." All are explicitly described as first-generation projections, not measured product performance. The density figure in particular is calculated from layout simulations using 2nm-process high-density SRAM as the baseline.
This comparison basis introduces major uncertainty in considering chip-count reductions for the Groq 3 LPU. Nagare Labs benchmarks against 2nm-generation high-density SRAM, which is not necessarily the same process generation or cell area as the SRAM in the Groq 3 LPU. A density ratio obtained under different design conditions cannot be applied directly to the capacity of the Groq 3 LPU. The figure of 1,024 falling to about 205 is therefore based on the assumption that a 5x density gain holds as-is for the same area, and it does not indicate the number of LPUs actually required.
Backing from real hardware is also still limited. Datta told The Register that the technology is currently at the laboratory prototype stage. Nagare Labs is looking for partners with R&D semiconductor fabrication facilities to move research done in university cleanrooms into a larger-scale manufacturing environment. It targets delivering working memory tile samples within four years and starting shipments of mass-production products within ten years. Counting from October 2026, that implies samples by around 2030 and mass production by around 2036, a long-term plan.
The $5 million raised is also early-stage money given the investment scale needed to commercialize semiconductor memory. At 150 yen to the dollar, it is about 750 million yen, and bringing a new memory technology to a mass-producible state will require continued investment in manufacturing facilities, equipment, process development, and reliability evaluation. The company's policy of using existing semiconductor manufacturing equipment is important for limiting that burden, but manufacturing costs and mass-production yields are still unknown.
There is also a gap between prototypes and product design in development progress. According to the company's public timeline, it succeeded in 2025 in prototyping a transistor structure stacked in four layers, and in 2026 obtained results on long-term stability. The first-generation product concept, on the other hand, envisions a design with six memory layers on a single die. In other words, while a four-layer prototype exists, the company has not yet manufactured the planned six-layer memory array or confirmed 5x the density of SRAM in measurements.
Datta himself acknowledges that commercializing new memory technology is difficult. Many memory startups have emerged in the past, and many never reached productization or market adoption. Even a superior technology may not be adopted in real systems if it cannot meet the strict specifications and reliability standards that semiconductor manufacturers demand.
Still, the reason to take Z2RAM's potential seriously is the size of the effect if the planned values are achieved. Even if the density gain falls short of the 5x target and reaches only half that, or 2.5x, a calculation focused solely on memory capacity suggests room to cut 1,024 LPUs to about 410. In other words, the idea that better storage density leads to fewer chips holds up, but how much benefit is obtained depends on measured performance. What can be assessed now is the possibility, not guaranteed product performance.
Standardizing 3D bonding and oxide semiconductor reliability are key to practical use
Gelsinger has pointed out that over the past 30 years, widely adopted memory technologies have centered on three types, SRAM, DRAM, and flash memory, and he expects Z2RAM could become a new option. But practical use faces challenges beyond storage density and access speed. One is how to connect it to the compute chip.
Z2RAM adopts a concept in which memory layers are stacked on a single die and that memory die is placed on top of the compute circuits of an AI accelerator. While the memory layers are formed together by deposition, integration with the compute chip requires 3D bonding technology. Co-founder Shimeng Yu told The Register that there is currently no standard specification for connecting new memory to AI accelerators. Making use of larger and faster memory requires technology that connects chips at high density, but the method has not been standardized.
AMD's 3D V-Cache is also in practical use as a technology for stacking SRAM on a CPU, but its connection method is based on AMD's proprietary design. For a wide range of semiconductor makers to adopt Z2RAM, in addition to compatibility with existing manufacturing processes and packaging technologies, electrical connection specifications, signal transmission, power delivery, and thermal design must be worked out. Without a common specification, Nagare Labs may have to develop its own interface and tune it for each company's accelerators. That burden will be an important factor in how widely the technology spreads.
The reliability of the memory cell itself is also a major challenge. Oxide semiconductors have advantages in operation at high temperatures and resistance to radiation, but they are prone to atomic defects inside the material. According to Datta, even a shift in a transistor's threshold voltage caused by the effect of just a few electrons could disturb the state of a memory cell. Threshold voltage is the reference voltage at which a transistor turns on, and its fluctuation directly affects the reliability of data retention and readout.
Nagare Labs says it is devoting substantial development resources to improving memory cell reliability in order to suppress this instability. Because AI accelerators process large volumes of data at high speed, memory malfunctions affect the reliability of results and the stability of the whole system. Beyond demonstrating operation in a single cell, it will be necessary to confirm error rates, data retention characteristics, tolerance to temperature changes, and long-term operational stability in large memory arrays.
On the manufacturing side, there is potential to use existing technology. According to Nagare Labs, the oxide semiconductors used in Z2RAM belong to the same family as materials mass-produced today in display manufacturing. The company also aims for a design that can be made with DUV lithography, using standard CMOS manufacturing processes and 300mm-wafer-compatible equipment to form the memory layers. If memory layers can be added without EUV lithography equipment, that opens an option for expanding storage capacity without depending on advanced lithography tools. However, being able to use existing materials and equipment is a separate matter from being able to mass-produce at high yield.
In judging Z2RAM's prospects, the conditions to confirm in future development are clear. Most important is whether Nagare Labs can actually achieve 5x the storage density of SRAM in the memory tile samples it is targeting within four years. If measured values fall short of that level, the LPU reduction estimated here cannot be expected as-is. It also matters whether operating speed, power consumption, and data retention time come close to the planned values.
In addition, whether 3D bonding specifications are put in place and joint design with the semiconductor makers developing AI accelerators advances will shape adoption. Even if the memory cell alone performs well, if integration with the compute chip proves difficult, the benefits at the whole-system level cannot be realized. Conversely, if actual samples confirm 5x the storage density and the issues of connection method and reliability are resolved, AI accelerators could place large-capacity, high-speed memory directly on top of their compute circuits.
Z2RAM's potential lies not in simply replacing SRAM, DRAM, or HBM, but in creating a new memory hierarchy in a domain where combining capacity and access speed has been difficult. For AI inference systems that have needed many chips because of memory capacity limits, it could lead to fewer chips and less data movement. How much of that effect is realized, however, depends on real-hardware performance and the maturity of manufacturing and packaging technology. Whether the company can show its density, speed, and power targets as measured values in upcoming sample development will be the first important test.