Research on Nagare Labs' new memory technology, Z2RAM, is drawing attention after a test cell retained data for more than 300 seconds at 85°C. On October 26, 2026, the company announced its concept for Z2RAM, a memory placed close to AI chips that aims to combine high speed with large capacity. But the 300-second figure is a data retention time, not a read speed. The research memory cell that achieved it also has a different structure from the Z2RAM the company aims to commercialize. Separating the performance demonstrated in research from the design projections made for the product is essential to assessing what this technology can really do.
In today's memory hierarchy, SRAM excels at low-latency access, while DRAM and HBM excel at holding large amounts of data. Z2RAM is being developed to fill the gap between them. It uses a "capacitorless" approach with no separate storage capacitor, and aims to deliver both speed and density by stacking multiple memory layers vertically. However, capacitorless does not mean the cell holds no charge. The 3T structure used in the research has three transistors, while the 2T structure in the product concept has two. This difference needs to be kept in mind when evaluating the memory density target the company has set.
300-second retention, 2.6 ns read and 5x SRAM density are separate metrics
The performance figures published in connection with Z2RAM come from different structures and different stages of validation. The retention time of more than 300 seconds at 85°C is a value measured in research using a 3T memory cell called FAB. The 2.6 ns read latency, by contrast, is a predicted value for an FAB design assuming a 7nm process, and the 5x density relative to SRAM is a first-generation performance target for a six-layer Z2RAM. These were not achieved simultaneously in the same memory cell.
Based on the official VLSI 2026 abstract and Nagare Labs' official website, the main figures can be summarized as follows.
| Metric | Structure / comparison basis | Validation stage | What the figure means |
|---|---|---|---|
| Retention of 300+ seconds at 85°C | FAB-type 3T gain cell | Measured | Data retention of a research memory cell |
| 2.6 ns read latency | FAB design assuming a 7nm process | Design prediction | Read speed of a scaled-down cell |
| 5x the density of SRAM | Six-layer Z2RAM vs. 2nm high-density SRAM | First-generation target / layout simulation | Density gain from the stacked structure |
This table is not a direct comparison of each technology's performance; it organizes differences in structure and validation stage. It has not been demonstrated that the 3T cell with 300-plus seconds of retention can also read in 2.6 ns or be manufactured at five times SRAM density. On its website, Nagare Labs also lists a speed 14 times that of DRAM and a read energy about one-third that of SRAM as first-generation predictions. These, too, are not benchmark results from actual products, and the read-energy prediction in particular does not support the conclusion that overall AI system power consumption would fall to one-third.
The FAB research was presented at the 2026 VLSI Symposium as session T18.4 and is not a newly published paper. The paper's DOI is 10.1109/VLSITechnologyandCir65830.2026.11577450. The public abstract outlines the measurement results and design predictions, but details such as sample counts, measurement error and retention-time variation are not available. Public information alone therefore does not show how reproducible the research cell's performance is.
Capacitorless, yet still storing charge: how Z2RAM works
On its official website, Nagare Labs describes Z2RAM's basic structure as "two transistors and a shield." Charge is stored on a storage node through a write transistor, and a read transistor detects its state. The company is aiming for non-destructive readout, in which the stored charge is not lost during a read. While the design omits the separate storage capacitor that conventional DRAM requires, it still relies on the charge and capacitance of the storage node.
This approach is a type of memory structure known as a "gain cell," characterized by separate read and write paths. Z2RAM aims to raise density through a "monolithic 3D" structure, in which such memory cells are stacked vertically within a single die. Unlike HBM, which stacks completed DRAM dies, the concept is to build the memory cells themselves in multiple layers during the semiconductor manufacturing process.
The FAB research cell that demonstrated retention beyond 300 seconds, meanwhile, uses a folded, asymmetric 3T structure. According to the VLSI 2026 abstract, the write side uses a non-overlapping gate structure to suppress unwanted capacitive coupling from the write word line to the storage node. On the read side, capacitive coupling is instead used actively, with voltage changes on the read word line boosting the storage node voltage. The aim is to reduce dependence on operation near the transistor threshold and improve tolerance to threshold-voltage variation.
The research measured a "memory window" of 1.48 V at a 1 V supply voltage. A memory window is the voltage difference used to distinguish between different storage states; it does not mean 1.48 V was supplied from the power source. The result indicates that boosting the voltage through capacitive coupling can secure a sensing margin during reads. However, it has not been demonstrated that measurements from this 3T structure can be reproduced in a 2T structure with fewer transistors.
Under what conditions could 300 seconds of retention make refresh unnecessary?
The public abstract of the FAB research names the last-level cache of a GPU as an intended use. This refers to the cache closest to main memory in the cache hierarchy. According to the abstract, performance predictions for a 7nm FAB design meet the no-refresh requirement for this use, assuming the maximum data lifetime found in AI workloads.
The key concept here is "data lifetime," meaning the period for which data stored in the cache is needed. If the data lifetime is shorter than the time a memory cell can hold its charge, the data may be usable without periodic refresh operations. In other words, longer retention is not unconditionally better; what matters is its relationship to how long data actually has to be held in the workload.
Nagare Labs' website includes both a statement that refresh frequency can be kept extremely low and one that refresh cycles become unnecessary. These cannot, however, be read as a guarantee that refresh is never needed in any use. Long retention does not mean non-volatility, and it has not been demonstrated that data can be stored with the power off.
Nor can the same conditions be applied to a GPU's last-level cache and to areas that store the KV cache or model weights during inference simply because both are AI-related memory. The required retention time differs by use, and cell retention also changes with operating temperature. The public abstract does not show the distribution of retention times across cells or characteristics at temperatures above 85°C. Judging how far refresh can be omitted requires comparing each use's data lifetime with the retention performance of the entire memory array at actual operating temperatures.
Heat dissipation and power delivery are the challenges of six-layer stacking
To commercialize the multilayer structure Z2RAM is aiming for, heat dissipation and power delivery matter as much as the performance of a single memory cell. One useful reference is a separate study of structures that stack 16 DRAM layers with logic. The paper "3-D Stacked HBM and Compute Accelerators for LLM" by Janak Sharda and colleagues was accepted by IEEE JXCDC in 2025, and the published accepted author version simulates thermal and power-delivery constraints under different stacking configurations. It is not, however, a study that tested Z2RAM itself.
The paper notes that heat dissipation is a key challenge when HBM is placed on top of logic, while voltage drop in the power delivery path is the key challenge when logic is placed on top of HBM. Removing heat generated by the logic requires securing thermal conduction paths, and supplying large currents stably requires limiting voltage drop from wiring resistance. Changing the stacking order alone cannot solve both problems; the design must account for both heat dissipation and power delivery paths.
In the HBM-on-logic model shown in Fig. 4 of the paper, assuming an upper DRAM temperature limit of 95°C, the logic's power density is limited to 220 W/cm². In a model with improved thermal conductivity in the back-end-of-line (BEOL) wiring layers, the allowable power density rose to 300 W/cm². The dimensions, thermal properties and other conditions used in the simulations are given in Tables I and II of the paper.
However, 95°C is simply the temperature condition set in this simulation; it is neither a standard upper limit common to all DRAM nor a heat tolerance measured on real devices. Nor can the gap between that and the 85°C at which FAB retention was measured be treated as Z2RAM's temperature margin. For the planned six-layer Z2RAM as well, the temperature conditions under which required retention can be maintained, and the logic operating power allowed under those conditions, need to be verified based on actual materials and stacking structures.
The key to commercialization: can a 2T array deliver both speed and retention?
Nagare Labs' October 26, 2026 announcement outlines plans to use materials suited to volume production, 300mm wafer manufacturing and BEOL processes. But turning a research-stage cell structure into a product requires manufacturing 2T memory arrays of the needed capacity and securing sufficient yield and operational stability. Of particular importance is how cell-to-cell variation and temperature changes from stacking affect read speed and retention time. Having a manufacturing approach intended for volume production is not the same as having verified the technology as manufacturable at volume.
Judging product-level performance would require results measuring read speed, retention time and read energy under the same operating conditions in a six-layer 2T array. Energy consumption including peripheral circuits, and temperature conditions in the stacked structure, would need to be evaluated as well as the memory cell alone. The public materials currently available do not include product-level data supporting the simultaneous achievement of these performance levels.
If the Z2RAM concept is realized, it could offer a new memory tier that needs less area than SRAM and is accessed with lower latency than DRAM, giving a way to increase the memory capacity placed near AI chips. But the long retention of a 3T research cell and design simulations alone are not enough to judge its feasibility. The biggest question for productization is whether a 2T array of practical capacity can meet speed, retention, energy consumption and thermal constraints in a stacked structure all at once.