In late September 2026, NuvaCore unveiled "Core First," a development approach in which work on the foundational design of a CPU core proceeds before the instruction set is decided.
In a video attached to the announcement, the company says more than 95% of the foundational IP that makes up a CPU core can be developed before the instruction set is finalized.
For its general-purpose CPU core, WarpCore, NuvaCore says it first designs the core itself, balancing performance, power efficiency and the area it occupies on the chip. It then selects an instruction set to suit the systems that it or its partners build.
In CPU development, the choice of instruction set architecture (ISA), such as Arm, x86 or RISC-V, normally has a major influence on the design from an early stage. Core First is an attempt to push that decision as late as possible while moving CPU core development forward.
However, being able to design much of a CPU core independently of the ISA is a separate matter from ensuring that the final CPU correctly supports the chosen ISA and runs existing software without problems.
To evaluate NuvaCore's claim, it helps to separate two questions: how much of the "95%-plus" design can really be shared, and how performance and validation costs change when the remainder is adapted to a specific ISA.
"Over 95%" does not mean the CPU is nearly finished
NuvaCore's announcement post says a "substantial portion" of the foundational IP of a CPU core can be developed before the instruction set is fixed.
The public transcript of the attached video makes this more specific: "more than 95% of the foundational IP of the CPU core."
IP here refers to the design assets used to implement a semiconductor's circuits and functions. The "95%" therefore does not mean that development of the entire chip is 95% complete.
What NuvaCore claims is that most of the foundational design assets that make up a CPU core can be developed before the ISA is settled.
ISA stands for Instruction Set Architecture, the specification that defines the instructions and registers visible to software, and how the CPU behaves when it executes those instructions.
NuvaCore is describing how far CPU internals can be designed before the ISA is chosen. It is not saying that WarpCore is already 95% complete.
Neither the announcement post nor the video explains what the 95% is measured against.
It is unclear whether the figure refers to the number of design blocks, the size of the RTL, circuit area or some other basis. Its relationship to development effort, including verification, physical design and software enablement, is also not stated.
The figure therefore cannot be used to estimate remaining development time or the effort needed to reach a product.
Based on the announcement and the company website, here is what is currently known:
| Item | What has been disclosed | What still needs confirming |
|---|---|---|
| Development sequence | Foundational CPU core IP is developed before the ISA is fixed | Which parts are ISA-independent and shareable, and which change once the ISA is chosen |
| "Over 95%" | NuvaCore's own description of the foundational core IP | How the 95% is calculated, and its relationship to circuit size, area and development effort |
| Main use | Sustained, heavy workloads in AI infrastructure and data centers | The workloads actually targeted, comparison points and measurement conditions |
| Design goals | Optimizing performance, power efficiency and chip area together | Performance, power consumption and core area measured under the same conditions |
| Product | Developing a general-purpose CPU core, WarpCore | Chosen ISA, manufacturing process, core configuration and availability |
What NuvaCore has concretely presented so far is a way of thinking about the order in which a CPU is designed.
Measured figures, such as how much faster WarpCore is than existing Arm, x86 and RISC-V CPUs, or how much it reduces power consumption and area, have not yet been published.
Choosing the ISA later does not remove its constraints
The idea of designing CPU internals somewhat separately from the ISA is not new.
High-performance x86 CPUs, for example, widely translate complex x86 instructions into finer-grained internal "micro-operations" and send that internal representation to the execution units.
In other words, the ISA seen by software and the "microarchitecture" that determines how the CPU executes those instructions internally are not the same thing.
But being able to translate into an internal representation does not mean the influence of the ISA can be ignored.
Ultimately, a CPU must behave as the ISA specifies from the software's point of view.
The research paper "Verifying x86 Instruction Implementations," which examines Centaur Technology's x86 CPU, covers methods for verifying that final behavior matches the x86 specification, from instruction decoding through translation to micro-operations and on to the execution circuits.
This is not research on WarpCore's design approach. Still, it illustrates that even when a CPU uses its own internal processing format, it must be confirmed that its behavior matches what the ISA requires.
The ISA's influence is also not limited to the decoder that reads instructions.
A representative example is the memory model, which defines the order in which multiple CPU cores access memory.
Under the RISC-V RVWMO specification, memory operations executed by one core may be observed by another core in an order different from the one written in the program.
Synchronizing multiple tasks correctly therefore requires controlling memory operation order with instructions such as FENCE.
For example, even if one core writes data and then sets a "done" flag, the order in which another core sees the data and the flag depends on the memory-ordering rules defined by the ISA.
Designing fast caches and memory circuits is not enough; behavior as seen by software must match the specification of the adopted ISA.
Even if Core First lets NuvaCore design many circuits before the ISA is fixed, it cannot skip this conformance verification later.
NuvaCore's own job listing for CPU designers covers a wide range of areas, including not only instruction fetch and decode but also execution units, load/store, memory management and caches.
The requirements include experience with RISC-V, Arm64 or x86, along with an understanding of how the ISA affects CPU microarchitecture design.
This suggests NuvaCore itself does not believe the ISA and the CPU's internal design can be completely separated.
However, it cannot be concluded from this listing that WarpCore will support all three of Arm, x86 and RISC-V.
How it differs from AMD's SkyBridge: what gets shared
There are past examples of trying to share as much hardware design as possible across different ISAs.
In May 2014, AMD announced a concept it called "ambidextrous computing."
One part was Project SkyBridge, a plan to make Arm and x86 processors pin-compatible so that processors with different ISAs could be used in the same system design.
Under that plan, the Arm version was to use Cortex-A57 and the x86 version Puma+.
In other words, the ISAs and the CPU cores themselves were already decided, and the aim was to share the outer system design, such as SoC peripheral functions and boards.
It was not a concept of changing a single CPU core to Arm or x86 later.
NuvaCore's Core First, by contrast, says it advances the foundational design of the CPU core itself first and defers the ISA decision.
Both the scope of what is shared and the timing of the ISA decision differ from SkyBridge.
SkyBridge is useful as a past example of trying to share design assets across products using different ISAs. But there is no basis for assuming WarpCore takes the same technical approach.
If NuvaCore clarifies which parts of the CPU internals are ISA-independent and which must be reworked after the ISA is chosen, it will become easier to evaluate Core First's technical character in concrete terms.
Founders with experience at NUVIA and Apple
In its April 15, 2026 public launch, NuvaCore introduced Gerard Williams III, John Bruno and Ram Srinivasan as founders and disclosed that it has received funding from Sequoia Capital.
On April 30, it announced that it had appointed David Williamson as senior vice president of hardware engineering. He previously worked at AMD and Arm, then spent more than a decade on CPU development at Apple.
Williams previously led CPU development at Apple and later served as co-founder and CEO of NUVIA, founded in 2019.
Qualcomm acquired NUVIA in 2021 for $1.4 billion. The CPU technology NUVIA had been developing was subsequently incorporated into Qualcomm's own CPU development.
The gathering of engineers with CPU design experience helps explain the background to NuvaCore's attempt to develop a new CPU core from scratch.
However, the team's résumés do not in themselves prove WarpCore's performance.
Nor does NUVIA's past acquisition by Qualcomm give grounds to assume NuvaCore is aiming to be sold to a large semiconductor company in the same way.
NuvaCore has not yet clarified its business model, such as whether it will sell finished processors or provide WarpCore to other companies as CPU core IP.
What is the value of choosing the ISA later?
The benefit NuvaCore describes for Core First is the ability to choose the ISA to fit the systems that it or its partners build.
If the main parts of a CPU core can be reused while the ISA is selected separately, it may become easier to develop CPUs that match a customer's existing software environment and system configuration.
At this point, though, this is only a design philosophy. No multiple WarpCore products using different ISAs, or specific customer contracts, have been announced.
What matters to customers is also not the mechanism of "choosing the ISA later" itself.
The real value lies in how much of their existing operating systems, compilers, libraries and applications they can use, and whether those run stably at high performance.
NuvaCore's job listing for a software validation lead also describes leading a validation organization covering firmware, operating systems, compilers and runtimes.
The role covers everything from the development stage using simulators and emulators to actual manufactured silicon, and includes validating problems that arise among the CPU, firmware, OS and compilers.
Of course, this describes future work in a job listing and does not show that WarpCore validation has already been completed.
Still, it makes clear that the work after choosing an ISA is not as simple as just adding a decoder.
Evaluating Core First will require real CPUs
WarpCore can be properly evaluated only once the ISA it adopts and the specific CPU configuration are known.
Beyond showing that an actual CPU runs operating systems and applications correctly, it will be necessary to see how well it sustains performance in long-running, high-load environments such as the AI infrastructure and data centers NuvaCore targets.
Comparisons with competing CPUs would need to measure performance, power consumption, performance per watt and the area occupied by the CPU core, using the same software and workload conditions.
It will also matter how many circuits must be redesigned, and how performance, area and development time change, when the same WarpCore foundation is extended to a different ISA.
If NuvaCore can show that most of a CPU core can be designed independently of the ISA while still adapting efficiently to multiple software environments in the end, Core First would be significant.
On the other hand, even if over 95% can be shared, a heavy burden of design and verification on the remainder would mean the figure alone cannot indicate development efficiency.
What this announcement presents is not the performance of a finished CPU but an idea for changing the order of CPU development itself. The real evaluation of WarpCore will depend on how concretely NuvaCore discloses its ISA, implementation and performance.