Supply-chain reports claiming that NVIDIA's next-generation architecture "Feynman" uses TSMC's A16 have shifted in substance over the past few months. In December 2025, DIGITIMES reported that NVIDIA was "the sole customer at the time," whereas in March 2026, Cnyes (鉅亨網) reported that A16 supply is limited, that NVIDIA cannot secure the volume it needs, and that only the most critical die will remain on A16 while some others move to N3P. Neither NVIDIA nor TSMC has officially disclosed Feynman's manufacturing node or the per-customer allocation.
Still, when you line up the domain A16 targets with the Feynman configuration NVIDIA presented at GTC 2026, the significance of these reports becomes clearer. This is not confirmed information that "Feynman adopted A16." Rather, it's a question of which dies use the new node—something that affects both the performance of the generation as a whole and the combination of products that can actually be manufactured.
The "sole customer" report has shifted to a mixed-node design
On December 1, 2025, DIGITIMES reported that NVIDIA was at that time the sole customer for A16, and that the Kaohsiung F22 P3 fab planned to begin A16 production for NVIDIA's roadmap in 2027. The same article also reported that equipment move-in was scheduled for Q2 2026. However, this was neither confirmed by TSMC or NVIDIA, nor was it an official plan corroborating allocation to a specific customer.
What Cnyes reported on March 22 adds a supply-constraint angle to the same adoption narrative. Because A16 capacity is insufficient, the report says, A16 will be used for the highest-priority die, while some other dies will be manufactured on N3P. TSMC stated it does not comment on market rumors or individual customers, and as of the article's publication, NVIDIA had not responded either.
This should not be read as "A16 has been secured" or "A16 has been monopolized." The December article reported an adopting customer; the March article reported that, even if adoption is proceeding, it may not be possible to put every necessary die on the same node. There is still no confirmed information connecting the two.
The capacity outlook cited in these reports doesn't carry the same weight as an official announcement, either. Cnyes cited an industry estimate that A16's monthly capacity would reach roughly 20,000 wafers by the end of 2027 and roughly 40,000 wafers in 2028. Meanwhile, the F22 P1/P2 monthly capacity figures reported by DIGITIMES are numbers for N2, with each building targeting 20,000–25,000 wafers—not A16 capacity figures. Mixing up what the numbers actually refer to can substantially change the supply outlook.
TSMC's statement that it "does not anticipate bottlenecks in ramping up capacity" doesn't directly refute this either. What the company said in its earnings call was that it expects to proceed with fab construction and capacity expansion as planned. How many units are allocated to which die for which customer during a given generation's ramp-up is information at a different level. Confirming the supply-constraint narrative reported here would require additional information showing either per-customer allocation or the configuration of actual products.
What backside power delivery frees up is headroom for signal routing
TSMC's A16 combines nanosheet transistors with a backside power delivery scheme it calls "Super Power Rail." By moving power-carrying interconnects to the back side of the wafer, the front-side routing resources become available for signal use, with the aim of suppressing IR drop—the voltage drop that occurs across the power network. TSMC states that its backside contact method preserves gate density, layout area, and device-width flexibility.
The comparison point is N2P. TSMC's targets are an 8–10% speed improvement at the same power, or a 15–20% power reduction at the same speed, with chip density up to 1.10x. These are process targets presented under separate comparison conditions—they don't mean that a Feynman product will simultaneously improve speed, power, and density across that entire range.
Even so, there's a clear reason A16 is discussed in connection with large dies for high-performance computing. TSMC itself explains that it's best suited to specific HPC products with complex signal routing and dense power delivery networks. In chips that handle compute units, memory, and networking in close proximity, where power and signals are routed becomes a design constraint in addition to transistor scaling.
Overlaying the March mixed-node report onto this official explanation, it seems reasonable to think that A16 would be prioritized for the die where it offers the most value. However, that is an inference drawn from the reported die allocation and A16's intended use—not a fact NVIDIA has explained as its design rationale.
Feynman's configuration goes beyond the GPU
At GTC 2026, NVIDIA introduced Feynman as the major architecture following Vera Rubin. The official presentation lined up not just the new GPU but also the Rosa CPU, LP40 LPU, BlueField-5, CX10, Kyber copper-interconnect/CPO scale-up, and Spectrum-family optical scale-out. At least as officially depicted, Feynman is not a single GPU product name but a platform generation spanning compute to networking.
Because of this, even if A16 is used for some Feynman-related die, that alone doesn't mean the entire GPU—much less the other chips making up the platform—shares the same node. In products composed of multiple chips, the requirements for compute load, I/O, power, and supply volume differ die by die. There is no basis for extending reports about leading-node adoption to the manufacturing specifications of the consumer GeForce lineup or the entire Feynman platform.
At minimum, the set of components shown at GTC is not a single die. The Rosa CPU, LP40 LPU, BlueField-5, and CX10 all serve different roles, while Kyber and the Spectrum family connect systems outside the compute die itself. If A16 mainly targets specific HPC products with complex power and signal routing, node selection could plausibly be decided per chip role as well. But NVIDIA has not explained which node applies to which component.
NVIDIA's official GTC 2026 presentation makes no mention of A16, N3P, TSMC by name, or allocation to any specific foundry. Feynman's official roadmap and the manufacturing reports from the supply chain may complement each other in places, but they are not confirmed at the same level.
Confirming product specs starts from mass-production readiness
TSMC plans to bring A16 to a mass-production-ready state and begin mass production in the second half of 2026. N2 entered mass production in Q4 2025. In the Q2 2026 earnings call, N2 accounted for 3% of wafer revenue, and TSMC expects N2 to ramp rapidly in the second half of 2026. A16's mass-production readiness and a customer's actual product launch are not the same event.
Design environment preparation is also progressing. As of July 10, TSMC has published A16 design reference flows and certification programs with Cadence, Synopsys, and Siemens EDA. These cover physical implementation, timing/power sign-off, and electromigration/IR drop. The scope also includes processes from DRC/LVS through RC extraction, simulators, and thermal analysis. Tool certification sets the groundwork for design work to proceed, but it does not indicate NVIDIA's tape-out, allocated manufacturing capacity, or the start of shipments.
There are distinct stages in the manufacturing process that can look similar but are not the same. The availability of a design flow indicates that EDA tools support A16. Mass-production readiness indicates that the foundry is prepared to productize the process, but it doesn't tell us which chip a specific customer has actually sent into mass production. Allocated manufacturing capacity for a customer, tape-out, mass production, and product shipment are all different states. Depending on where a given piece of information falls among these, it carries different weight as confirmation of Feynman's adoption.
TSMC raised its 2026 capital expenditure to US$60–64 billion, with 70–80% earmarked for advanced process technology. The company also outlined plans to build 13 advanced process and advanced packaging fabs in Taiwan over the coming years, stating that it does not anticipate bottlenecks in its capacity expansion plans. Even so, this statement pertains to the execution of the expansion plan itself—it neither confirms nor denies whether sufficient capacity can be allocated to any individual A16 customer.
Settling the relationship between Feynman and A16 will require material that goes beyond announcements of mass-production readiness. Will NVIDIA disclose the target products and dies? Will TSMC disclose customer names? Will the manufacturing node of actual chips be made public? Even after A16's ramp-up in the second half of 2026, that confirmation gap between the reported adoption narrative and actual product specifications will remain.