Jeff Pu, an analyst at GF Securities, has said NVIDIA may use Intel's Foveros for back-end packaging of its AI accelerators from the second half of 2028. In January 2026, Taiwan's DigiTimes reported that NVIDIA was considering having Intel manufacture the I/O die for Feynman and handle packaging for about 25% of it, and the packaging method it named was EMIB. The official materials reviewed show these points of contact between the two companies: RAMP-C in July 2023, joint development and a $5 billion investment in September 2025, and the adoption of Xeon 6 in the DGX Rubin NVL8 in March 2026. None of them describes an AI GPU packaging contract. The open questions are how well the 2028 timing fits Intel's published plans, and how to read the difference in the reported method names.
January's report said EMIB, October's note says Foveros: how to read the difference in names
Pu's note was reported on October 9. What was relayed boils down to one point: NVIDIA may use Intel's Foveros for AI accelerator back-end packaging from the second half of 2028. The note reportedly says NVIDIA could become involved through Foveros around the same time Intel's 14A enters volume production in the second half of 2028. Details are sparse, and the note is said to broadly corroborate the January report. The reported content includes neither the target product name nor which type of Foveros is meant.
The comparison point is the DigiTimes report of January 28, 2026. The outlet said NVIDIA was considering manufacturing Feynman's I/O die on Intel 18A or 14A and packaging about 25% of Feynman with EMIB at Intel's New Mexico site. The main GPU die was said to remain with TSMC. The packaging method going to Intel was EMIB, a different name from the Foveros in the current note. It is the press, not the note, that links the Feynman product name to this note.
The difference in names cannot be read as the same source changing its view. The January report came from DigiTimes and the October note from Pu, so the sources differ. EMIB and Foveros are also not mutually exclusive: Intel's materials include EMIB 3.5D, which connects stacked Foveros chips with EMIB bridges.
Speculation about NVIDIA and Intel has not moved in one direction, either. In December 2025, Reuters reported that NVIDIA had run evaluation tests on Intel 18A and then stopped advancing talks toward adoption. About a month later, DigiTimes reported consideration of 18A or 14A, which points the opposite way. Both remain at the report stage and cannot be treated as established fact.
EMIB, Foveros and CoWoS: differences in how dies connect and when they reach volume
Back-end packaging refers to the process of wiring dies made in the front-end onto a substrate or interposer and assembling them into a single package. AI accelerators need GPU dies and memory placed close together and linked with wide bandwidth, and TSMC's CoWoS-S does this on a silicon interposer of up to 3.3 reticles (about 2,700 mm²). At its earnings call on July 16, 2026, TSMC CEO C.C. Wei reportedly said tight packaging capacity is constraining customer growth.
Intel's EMIB connects only the edges of adjacent dies using small silicon bridges embedded in the substrate. It differs from CoWoS-S in that it does not use a full interposer.
Even when reported under the Foveros name, Intel's materials divide it into two families: Foveros 2.5D (Foveros-S and Foveros-R), which places multiple dies side by side on a passive base die that handles wiring, and Foveros Direct 3D, which stacks dies vertically on an active base die using copper-to-copper hybrid bonding. Which one is meant changes the design assumptions.
| Method | Connection direction | Interposer, etc. | Interconnect pitch | Volume production / production readiness | Use (as stated in company materials) |
|---|---|---|---|---|---|
| EMIB | Lateral | Silicon bridge embedded in the substrate | Not stated | In volume production since 2017 | Logic-to-logic and logic-to-HBM connections |
| EMIB-T | Lateral | EMIB bridge with added through-silicon vias (TSV) | Not stated | Not stated | Same category as EMIB |
| Foveros-S 2.5D | Side by side on a passive base die | 4-reticle silicon interposer | 36μm (microbump) | In volume production since 2019 | For client |
| Foveros-R 2.5D | Side by side on a passive base die | No silicon interposer; connected via redistribution layer (RDL) fan-out | 36μm (microbump) | Production readiness in 2027 | For client and cost-sensitive segments |
| Foveros Direct 3D | Active dies bonded vertically | Active base die | Under 10μm (hybrid bonding) | Not stated | For client and data center. Available only on Intel Foundry process nodes |
| CoWoS-S | Lateral | Silicon interposer up to 3.3 reticles (about 2,700 mm²) | Not stated | CoWoS overall in volume production since 2012 | For HPC and AI (stated for CoWoS overall) |
| CoWoS-L | Lateral | RDL interposer and local silicon interconnect (LSI) bridges | Not stated | 3.5-reticle products in volume production since 2024 | For large HPC products |
The table lists only values found in official technical materials from Intel Foundry and TSMC; "Not stated" marks fields where the official materials reviewed give no value.
In Intel's materials, Foveros 2.5D is also described as a stacking technology that mounts dies on a base, but the base carries only wiring, and it is Foveros Direct 3D that bonds active dies vertically. In Foveros-S 2.5D and Foveros-R 2.5D, the multiple dies on top sit side by side. The redistribution layer and local silicon bridges that CoWoS-L combines in one package are close to Intel's Foveros-R and EMIB. This is the author's arrangement from placing the two companies' materials side by side, not a classification Intel itself makes.
The stated uses also differ by method. Foveros-S is described as for client, Foveros-R as for client and cost-sensitive segments, and the technical brief for Foveros Direct 3D cites designs for AI accelerators and HPC while saying it is available only on Intel Foundry process nodes. The January report said the main GPU die would remain at TSMC, and the materials do not say whether Foveros Direct 3D could be used in that configuration.
The type of Foveros Pu means has not been reported, and this table does not indicate the method NVIDIA would adopt. Reticle multiples and interconnect pitch are not values that directly show superiority in performance or cost. The correspondence between publication timing and definitions for Foveros-S's 4 reticles and CoWoS-S's 3.3 reticles cannot be confirmed, so which is larger cannot be compared.
In a January article, Tom's Hardware analyzed that a Feynman-class product would draw power in the 5–6 kW class by its estimate, which EMIB could not supply. Foveros can handle multi-kW power delivery, but packaging Feynman with Foveros Direct 3D would require redoing a GPU design built for TSMC's CoWoS-L, the outlet said. It considers redesigning a large GPU for Foveros unrealistic and thinks NVIDIA will likely wait for TSMC to start advanced packaging in the US in the late 2020s. It also writes that Intel could win packaging orders for products such as the Vera CPU first.
In an official article on July 29, 2026, Intel explained that the latest generation EMIB-T in 2026 delivers power through the inside of the bridge. The outlet's point about insufficiency concerned EMIB, and whether EMIB-T's power delivery meets the same requirement cannot be determined by setting the two statements side by side.
Points of contact in the official materials reviewed, and the absent packaging contract
The oldest point of contact goes back to July 18, 2023. Intel announced that Boeing and Northrop Grumman had joined RAMP-C, a US Department of Defense program, and named NVIDIA, Qualcomm, Microsoft and IBM as existing customers. Customers design and manufacture prototype chips on Intel 18A. NVIDIA was named only as one of the customers working on 18A prototype chips, and the announcement contains no mention of AI GPU manufacturing or packaging.
The next point of contact is the September 18, 2025 partnership. NVIDIA and Intel announced they would jointly develop data center and PC products across multiple generations. Intel will manufacture custom x86 CPUs for NVIDIA connected via NVLink and productize x86 SoCs integrating NVIDIA RTX GPU chiplets. NVIDIA will invest $5 billion in Intel common stock at $23.28 per share. At the October 6, 2026 market rate of 1 dollar = 158 yen, that is about 790 billion yen.
In the announcement, Intel CEO Lip-Bu Tan said that combining Intel's data center and client product lines with its process technology, manufacturing and advanced packaging capabilities would complement NVIDIA's strengths in AI and accelerated computing. Advanced packaging is mentioned, but nothing says AI GPU back-end packaging would be outsourced.
At the joint press conference on September 18, 2025, NVIDIA CEO Jensen Huang said "Intel has Foveros multi-technology packaging capability," Tom's Hardware reported. The use Huang described was an SoC connecting NVIDIA GPU chiplets and Intel CPUs in one package, and the outlet's article does not reveal any relationship to AI GPU packaging outsourcing or to the method Pu's forecast refers to.
On March 16, 2026, in conjunction with GTC 2026, Intel announced that Xeon 6 would be used as the host CPU in NVIDIA DGX Rubin NVL8. The adoption builds on the Xeon 6776P in the Blackwell-generation DGX B300; it is a CPU product supply, not a packaging contract.
According to reports based on Intel's filings, the FTC granted early termination of the HSR Act waiting period on December 18, 2025, and the acquisition of about 214 million shares was completed on December 26.
In the table below, "Official" means the company's own announcement, "Official (via press)" means executive statements or filings confirmed through press reports, and "Speculation" means reports or analyst views.
| Date | Event | Category |
|---|---|---|
| July 18, 2023 | Intel names NVIDIA as an existing RAMP-C customer (Intel 18A prototype chips) | Official |
| January 2024 | NVIDIA reported to have chosen Intel's foundry division for GPU back-end packaging (Taiwan's Economic Daily News report, relayed by Tom's Hardware) | Speculation |
| September 18, 2025 | NVIDIA and Intel announce joint development and $5 billion investment | Official |
| December 24, 2025 | Reuters reports NVIDIA stopped considering adoption after evaluation testing of Intel 18A | Speculation |
| December 26, 2025 | Share acquisition for the investment completed (report based on Intel's filings) | Official (via press) |
| January 28, 2026 | DigiTimes reports Feynman I/O die considered for 18A/14A and about 25% for EMIB | Speculation |
| March 16, 2026 | Intel announces Xeon 6 adoption in NVIDIA DGX Rubin NVL8 (host CPU) | Official |
| March 16, 2026 | Feynman presented as a 2028 generation at GTC 2026 (per Jon Peddie Research) | Official (via press) |
| July 16, 2026 | TSMC's Wei says back-end capacity is tight and welcomes packaging by other companies | Official (via press) |
| July 23, 2026 | Intel's Tan states at earnings call that 14A volume ramp is set for 2028 | Official (via press) |
| August 26, 2026 | Intel CFO Zinsner tells Deutsche Bank conference packaging revenue will contribute steadily in 2028 | Official (via press) |
| October 9, 2026 | Report that Pu's note points to possible Foveros use from the second half of 2028 | Speculation |
Speculation about NVIDIA and Intel manufacturing and packaging has been reported at least four times since January 2024, one of which reported that consideration of adoption had been dropped. But the points of contact between the two companies in the official materials reviewed are RAMP-C in July 2023 (Intel 18A prototype chips), joint development and the $5 billion investment on September 18, 2025, and Xeon 6 host CPU adoption in March 2026, and none includes AI GPU packaging outsourcing.
The four reports counted are the January 2024 Economic Daily News, the December 2025 Reuters, the January 2026 DigiTimes, and Pu's current note. The confirmation of absence is limited to NVIDIA's September 18, 2025 announcement, Intel's second-quarter earnings materials, the RAMP-C announcement and the Xeon 6 adoption announcement. The Economic Daily News and DigiTimes reports both remain at the report stage.
Intel's 14A volume production and packaging revenue plans converge on 2028
Intel's second-quarter 2026 revenue was $16.128 billion, and the Intel Foundry division posted $5.765 billion. The Foundry figure includes inter-segment transactions and is not revenue from external customers. CEO Lip-Bu Tan named "CPUs, ASICs, advanced packaging and the wafer foundry network" as growth areas, and CFO David Zinsner said investment in equipment, cleanrooms and substrates will increase significantly. During the quarter, on June 18, Intel appointed Seok-Hee Lee as head of advanced packaging.
At the July 23 earnings call, Tan said Intel formally decided in the second quarter to begin volume ramp of 14A in 2028. According to Tom's Hardware, 14A production in 2028 starts with Intel's own products. In a June 8 post on X, Pu said he expects Intel's front-end capacity to grow by 2028 year-end by 80% on Intel 3 versus end-2026 and 100% on 18A. These, including 14A, are plans and forecasts for the front-end (wafer manufacturing) and are separate from the back-end work Foveros handles. The two meet at the point where the January report named 18A and 14A as candidates for I/O die manufacturing.
According to TrendForce, at the Deutsche Bank conference on August 26, 2026, CFO Zinsner said advanced packaging revenue centered on EMIB-T would start in the second half of 2027, contribute steadily in 2028, and reach full scale in 2029. He said it could be a multi-billion-dollar annual opportunity per customer, and cited targets of about 40% gross margin and about 30% operating margin.
While 14A's volume ramp is in 2028, the packaging revenue ramp is placed earlier, in the second half of 2027. However, this outlook is a plan centered on EMIB-T and is not described as a Foveros revenue plan. No customer names were given.
There are numbers on the manufacturing site side, too. Intel's Rio Rancho, New Mexico site (Fab 9) has scaled packages up to 8 times the industry-standard reticle size and aims for more than 12 times by 2028. It has 2,700 employees and 500 suppliers, and Foveros assembly is also performed at the site. This multiple is an indicator of overall package size and is distinct from the interposer reticle multiples in the table above.
Expanding back-end capacity also requires securing substrates. At a J.P. Morgan conference in May 2026, Tan said substrate supply is extremely tight, that four Taiwanese and two Japanese companies are seeking advance commitments, and that he asked customers considering EMIB-T to take part in prepayment for substrates. The names of the two Japanese companies were not included in his remarks, but in 2025 Ibiden and Shinko Electric Industries were reported as partners for EMIB substrates. Ibiden resolved in February 2026 on a capital investment plan of about 500 billion yen for its electronics business for fiscal 2026–2028, and will begin sequential volume production of IC package substrates for AI servers and other uses from fiscal 2027. The plan does not say it is for Intel or NVIDIA.
At the same earnings call where he discussed tight back-end capacity, Wei also reportedly said TSMC would welcome competitors handling packaging of customers' front-end wafers. TSMC will devote 10–20% of its 2026 capital expenditure to advanced packaging, testing, masks and more. All of these are 2026 statements and plans and do not address the 2028 outlook or any change in NVIDIA's outsourcing partner.
Feynman's timing comes from Jon Peddie Research. NVIDIA presented Feynman as a 2028 generation at GTC 2026 on March 16 and reportedly said it would use 3D die stacking and TSMC's A16. NVIDIA has not disclosed the division of manufacturing, and this information does not corroborate Foveros adoption.
The three items converging on 2028 are Intel's 14A volume ramp, the steady contribution of packaging revenue that Intel expects, and Feynman as a reported 2028 generation. None of the three is a statement that NVIDIA will use Intel's back-end packaging; the timing match shows only that the forecast is not contradicted.
What would make the forecast verifiable: an announced contract and a named method
Pu's forecast becomes verifiable when NVIDIA or Intel announces an AI GPU back-end packaging contract and names the method. If the method is Foveros Direct 3D, the question is how the condition in Intel's technical brief, "available only on Intel Foundry process nodes," squares with where the main GPU die is made. If it is EMIB-T, that is the EMIB lineage the January report cited and also the method CFO Zinsner placed at the center of revenue.
Production readiness for Foveros-R 2.5D and the start of Intel's packaging revenue are both placed in 2027, but the former is for client and cost-sensitive segments and the latter is an EMIB-T-centered plan, so neither indicates when an announcement for NVIDIA's AI GPUs might come. With an announcement, it would be possible for the first time to check in official wording which of the two reports, January's EMIB or October's Foveros, came closer.