NVIDIA has underwritten $3.5 billion of MediaTek's convertible bonds. On August 31, 2026, the two companies announced an expanded collaboration to integrate custom AI accelerators into NVIDIA's NVLink interconnect fabric and racks. As hyperscalers increase their use of in-house chips, dependence on NVIDIA GPUs could decline. In response, rather than monopolizing the compute die itself, NVIDIA is moving to control the shared foundation of interconnects, memory, and racks that other companies' XPUs will use. The role of converting that pathway into mass-producible semiconductors falls to MediaTek's advanced packaging capabilities.
The $3.5 Billion Is Not an Equity Stake, but a Five-Year Convertible Bond
The $3.5 billion NVIDIA underwrote represents 89.7% of MediaTek's total $3.9 billion convertible bond issuance. According to MediaTek's material information disclosure, the bonds are scheduled for issuance on September 8, 2026, carry a 0% interest rate, have a five-year term, and mature on September 8, 2031. NVIDIA has not immediately acquired MediaTek common shares. At the time of issuance, NVIDIA becomes a bondholder with the right to convert to equity if certain conditions are met.
The initial conversion price was set at NT$4,513.75 per share — 115% of the reference closing price of NT$3,925 on August 31, a 15% premium. Even if the entire $3.9 billion were converted within the fiscal year, MediaTek indicates the maximum dilution rate would be only about 1.67%. Therefore, characterizing this transaction as an NVIDIA acquisition of MediaTek or a takeover of control would not be accurate.
On the other hand, the fact that NVIDIA underwrote roughly 90% of a zero-interest, five-year bond issuance signals that the two companies have aligned their interests over a timeframe longer than a single product generation. MediaTek secures dollar-denominated funding without interest burden, while NVIDIA retains the option to convert to equity according to contract terms. However, the disclosed use of funds is described only as "foreign currency-denominated material procurement needs." How much will be allocated to CoWoS production capacity, HBM, or ABF substrates is not disclosed. The relationship to hiring is also unclear, and the $3.5 billion cannot be regarded as a direct investment in advanced packaging.
From 2025 Participation Announcement to Joint Design of Mass-Production Pathways
The relationship between MediaTek and NVLink Fusion did not begin with this announcement. NVIDIA had already named MediaTek as an early adopter alongside Marvell and Alchip in May 2025. Arranging subsequent developments chronologically reveals a process in which NVIDIA has drawn custom silicon from a peripheral, interoperable feature into a core business it is willing to invest capital in.
| Date | NVIDIA's Move | Element Added to Custom AI Infrastructure |
|---|---|---|
| May 18, 2025 | Announced NVLink Fusion, listing MediaTek as an early adopter | Entry point connecting third-party XPUs to NVLink |
| March 31, 2026 | Invested $2 billion in Marvell | Collaboration on custom XPUs, optical interconnects, and networking |
| August 26, 2026 | Added NVHBM to NVLink Fusion | Custom HBM base die and memory controller |
| August 31, 2026 | Underwrote $3.5 billion of MediaTek convertible bonds | Joint infrastructure spanning design through rack |
MediaTek was already announced as an early adopter of NVLink Fusion in May 2025, so what is new in August 2026 is not initial participation but rather the expansion into a $3.5 billion capital relationship and a mass-production foundation that includes NVHBM. Adding the $2 billion NVIDIA disclosed for Marvell and the $3.5 billion for MediaTek in 2026 totals $5.5 billion, but the former is an investment while the latter is a convertible bond — these are not the same type of transaction. Still, the pattern is clear: NVIDIA has successively funded two leading companies that design custom XPUs.
The joint announcement also expanded collaboration on the technical side. MediaTek designs interconnects, memory, and packaging tailored to customers' XPUs, adjusting for performance and power consumption. NVIDIA provides Fusion chiplets, NVLink-C2C, and NVHBM, with MGX racks and networking positioned beyond that. The plan is to prepare combinations that have been pre-validated for design, certification, and system verification, allowing custom XPUs to track future NVIDIA architectures.
Accepting Custom XPUs While NVIDIA Retains Control of Rack Standards
Speaking to TechCrunch, NVIDIA's Dion Harris stated, "We are an AI infrastructure company." This statement succinctly captures the intent of the deal. Customers are pushed toward differentiating in the realm of compute logic, while NVIDIA and MediaTek supply memory and interconnects around it. The aim is to standardize even racks and operational infrastructure.
| Layer | Primary Designer | What NVLink Fusion Standardizes |
|---|---|---|
| Workload and proprietary IP | Hyperscalers, AI companies | Customer-specific compute methods are preserved |
| Custom XPU | Customer and MediaTek | MediaTek productizes logic and physical design |
| Packaging and HBM | MediaTek, NVIDIA, manufacturing/memory partners | Integrates Fusion chiplets, NVHBM, SerDes, I/O |
| In-rack interconnect | NVIDIA | Utilizes NVLink, NVLink-C2C, NVLink Switch |
| Rack and data center | NVIDIA and system partners | Shares MGX, networking, power, cooling, and management systems |
Under this division of labor, cloud companies need not handle everything with GPUs. They can use XPUs tailored for specific training or inference tasks while sharing rack footprint, power, and cooling infrastructure with NVIDIA GPUs. Networking and management systems can also be unified. AWS's plan to adopt NVLink Fusion and NVHBM for its next-generation Trainium chips, integrating them into shared racks with NVIDIA GPUs, is a concrete example of this.
For NVIDIA, even if its own GPUs cede some workloads, demand for the NVLink and CPU-inclusive interconnect infrastructure can be preserved. Switches, networking, and management software also become sales opportunities. Moreover, if GPUs and XPUs can be swapped within the same facilities, cloud companies avoid having to rebuild data centers for each chip type. However, NVLink Fusion pricing, how much revenue NVIDIA earns from which components, and revenue sharing with MediaTek have not been disclosed. The "toll booth" metaphor explains the strategy, but the toll amount remains unknown.
Advanced Packaging as the Substance of the Partnership
The joint announcement cited multi-die configurations and advanced packaging as conditions for mass-producing custom XPUs, incorporating high-speed SerDes, HBM, I/O, and scale-up interconnects. Even after logic circuits are completed, unless Fusion chiplets and HBM can be arranged on an interposer or substrate with signal, power, and thermal characteristics verified, they cannot enter a rack. Here, MediaTek's role expands from design proxy — attaching NVIDIA's IP to a customer's die — to system integration encompassing manufacturing and supply chains.
On the same August 31, MediaTek's Vice President of Advanced Packaging, former TSMC executive Shang-yung Hou, stated that the company must urgently strengthen this field and continue hiring. MediaTek has also disclosed in earnings briefings that it is investing in two packaging methods, explaining that next-generation AI ASICs will require increased value delivery in both silicon and packaging. The reinforcement of advanced packaging talent and the expanded collaboration with NVIDIA reflect the same mass-production challenge, viewed from both organizational and sales strategy angles.
NVHBM also delves deeply into packaging design. NVIDIA claims it can boost bandwidth per stack by up to 30% compared to standard HBM4e, reduce HBM power consumption by up to 15%, and increase the area available for compute dies by up to 25%. This is because part of the memory controller function is moved to the HBM base die, changing circuit area on the XPU side and interposer wiring. These are NVIDIA's own published figures, not third-party measurements of mass-produced products. Nevertheless, it is clear that NVLink Fusion extends beyond mere interconnect standards to dictate die placement and HBM selection.
There are also boundaries to what money alone can solve. Even if MediaTek secures dollar funding to purchase materials, advanced packaging capacity at foundries and assembly companies, HBM and substrate supply, and initial mass-production yields do not automatically increase. The $3.5 billion becomes a buffer supporting mass production, but mass-production capability itself only emerges when designers, manufacturers, and material suppliers move in sync on the same timeline.
Subordination to NVLink, or Dual Support?
MediaTek explicitly states on its official pages that it supports both the industry-standard UALink and UEC, as well as the proprietary NVLink. No exclusivity clause is indicated in this announcement. It cannot be confirmed that NVIDIA has entirely enclosed MediaTek's custom ASIC business; what can be said from public information is only that the pathway has been strengthened for customers who choose NVLink.
The competing framework, UALink, advocates an open standard connecting up to 1,024 accelerators at 200Gbps per lane. If customers prioritize multi-vendor interoperability, MediaTek can design UALink-compatible XPUs. On the other hand, if customers prioritize reducing development time and mass-production risk, and quickly integrating into the same racks as NVIDIA GPUs, NVLink Fusion — which has pre-validated the process of implementing compute dies and HBM and extending high-speed interconnects to the rack — becomes more advantageous. Advanced packaging design capability is necessary either way, but the chosen interconnect standard determines who holds leadership over the rack.
The success or failure of this $3.5 billion deal should be judged not by the scale of the convertible bond, but by the resulting products. Can MediaTek mass-produce, as planned, the AI ASICs it projects will generate approximately $2 billion in 2026, and can it stably integrate Fusion chiplets, NVHBM, and advanced packaging in subsequent projects? Furthermore, how will customers choose between NVLink and UALink, and to what extent will they differentiate the use of NVIDIA GPUs and custom XPUs within the same racks? When these details are disclosed, it will become possible to measure whether NVIDIA has successfully transformed the wave of custom silicon into growth for its own infrastructure.