NVIDIA's current "Vera Rubin NVL72" product specifications list per-GPU HBM4 memory bandwidth of 19.2TB/s and GPU-to-GPU NVLink bandwidth of 3TB/s. Checked on October 27, 2026 (JST), these figures are about 13% and about 17% lower, respectively, than those in an official technical explainer the company published on July 21. HBM4 capacity remains 288GB, but capacity and bandwidth are different metrics, and a change in bandwidth may affect AI processing performance. Separately, for HGX, which carries eight GPUs, the figures in the official specifications differ by up to 26%. That figure is not the same as the specification change rate for NVL72, nor as an actual drop in AI performance, so product configurations and comparison conditions need to be evaluated separately.
Vera Rubin NVL72: HBM4 bandwidth at 19.2TB/s, NVLink at 3TB/s
NVIDIA's July 21 technical explainer on the Rubin GPU described HBM4 memory with 288GB of capacity and bandwidth of up to 22TB/s. NVLink bandwidth was given as 3,600GB/s, or 3.6TB/s. The January 5 explainer on the Rubin platform also gave HBM4 bandwidth of 22TB/s and NVLink bandwidth of 3.6TB/s, and it explicitly states that the NVLink figure is bidirectional. However, the current Vera Rubin NVL72 product specifications, covering a system with 72 GPUs and 36 CPUs, keep HBM4 capacity at 288GB but list lower bandwidth figures than before.
| Item | January/July official descriptions | Current NVL72 per-GPU specs | Difference in stated values |
|---|---|---|---|
| HBM4 capacity | 288GB (July) | 288GB | No change |
| HBM4 bandwidth | 22TB/s | 19.2TB/s | 12.7% lower |
| NVLink bandwidth | 3.6TB/s | 3TB/s | 16.7% lower |
The reductions are calculated against the earlier stated values. HBM4 bandwidth is (22 − 19.2) ÷ 22 × 100, or about 12.7%, and NVLink bandwidth is (3.6 − 3) ÷ 3.6 × 100, or about 16.7%. These are comparisons of specification values published by NVIDIA, not results of performance measurements on actual hardware. Even though HBM4 capacity is unchanged at 288GB, a different bandwidth for reading and writing data could affect workloads where memory access determines performance.
The current specifications list the Superchip, which combines two GPUs, at 576GB of HBM4 capacity, 38.5TB/s of bandwidth and 6TB/s of NVLink bandwidth. For the full NVL72 rack with 72 GPUs, the figures are 20.7TB, 1,400TB/s and 216TB/s, respectively. However, the stated values for a single GPU, the Superchip and the full rack include rounding, so 38.4TB/s (twice 19.2TB/s) differs slightly from the Superchip's 38.5TB/s. Likewise, even if a single-GPU bandwidth multiplied by 72 differs from the rack-level figure, that alone does not indicate a further performance drop or specification change.
HGX shows a gap of up to 26%, with single-GPU and eight-GPU specs inconsistent
A larger gap appears in the HGX platform, which carries eight GPUs. NVIDIA's current HGX product page lists total HBM4 capacity of 2TB and bandwidth of 130TB/s for configurations combining a Vera CPU or x86 CPUs with eight Rubin SXM GPUs. Yet the per-GPU specifications on the same page still carry the earlier figures of 288GB of HBM4 capacity and 22TB/s of bandwidth. Multiplying the single-GPU 22TB/s by eight gives 176TB/s, leaving a 46TB/s gap against the eight-GPU stated value of 130TB/s.
Calculated against 176TB/s, the difference is (176 − 130) ÷ 176 × 100, or about 26.1%. In other words, the "up to 26%" figure comes from comparing the single-GPU bandwidth listed on the same HGX product page, multiplied by eight, with the stated bandwidth of the eight-GPU configuration. It is not a like-for-like comparison of past and current HGX products, nor a measured performance drop. NVIDIA has not explained why this gap exists, and it cannot be assumed that NVL72 bandwidth fell by a similar proportion.
The October 2026 edition of NVIDIA's official HGX datasheet also lists the eight-GPU configuration with 2TB of HBM4 capacity, 130TB/s of bandwidth and 24TB/s of NVLink bandwidth. The 130TB/s figure therefore appears not only on the HGX product page but in another official document. That said, the discrepancy with the 22TB/s single-GPU figure has not been resolved. Note that "Oct26" in the datasheet denotes the October 2026 edition and does not mean the specifications changed on October 26.
It is worth noting that the NVL72 single-GPU figure of 19.2TB/s cannot necessarily be applied to HGX as is. Conversely, dividing HGX's 130TB/s by eight to get 16.25TB/s cannot be taken as the confirmed single-GPU bandwidth of Rubin. For HBM4 capacity, 288GB per GPU and 2TB for eight GPUs coexist, but differences in units and rounding make it inappropriate to calculate an exact reduction rate from them. Whether the differences reflect product configurations or simply inconsistent updates to published materials cannot be determined from the information currently available.
How might HBM4 and NVLink bandwidth affect AI performance?
HBM4 bandwidth matters because large language model (LLM) inference performance depends not only on the GPU's compute capability but also on how fast data can move to and from memory. When a generative AI model produces tokens sequentially, it reads the model weights and also accesses the KV cache, which holds information about past tokens. HBM4 capacity determines how much of the model and KV cache can be held, while bandwidth relates to how quickly that data can be read and written. The emphasis NVIDIA placed on memory system efficiency in its July technical explainer reflects the importance of data transfer in such generation workloads.
Compared with the earlier HBM3e, HBM4 doubles the width of the memory interface. This change increases the amount of data that can be transferred in parallel between the GPU and memory, but actual bandwidth depends not only on interface width but also on factors such as signal transfer speed. Simply adopting HBM4 therefore does not guarantee the originally announced 22TB/s of bandwidth or the effective performance that would go with it.
In workloads bottlenecked by reading data from memory, differences in HBM4 bandwidth may affect performance. However, the share of total processing time spent waiting on memory access varies with the model's structure, batch size, the lengths of input and generated tokens, how the KV cache is used, and other factors. Whether GPU compute and memory access can be efficiently overlapped also matters. It therefore cannot be concluded that a 12.7% lower stated memory bandwidth means AI token generation speed falls by the same proportion.
NVLink, meanwhile, handles high-speed data transfer between GPUs. NVIDIA's January explainer cites as main uses Mixture of Experts (MoE), which routes work to selected expert networks, as well as collective communication and synchronization between GPUs. When a large AI model is distributed across multiple GPUs, inter-GPU communication bandwidth is an important factor in processing efficiency. However, the required communication volume depends on how the model is partitioned, and the effect of a bandwidth difference on actual performance also varies with how far communication and computation can run in parallel.
The Rubin platform also includes paths other than GPU-to-GPU NVLink, such as NVLink-C2C connecting CPUs and GPUs and the external networking linking servers and racks. In the current NVL72 specifications, the Superchip's NVLink-C2C bandwidth is 1.8TB/s, and the rack's external network bandwidth is 32.4TB/s bidirectional. These are separate communication paths, however, and external network bandwidth cannot be added to HBM4 or inter-GPU NVLink bandwidth to make up for a performance difference. Assessing the real impact requires understanding which path a workload uses and where communication waits occur.
Real-world AI performance unconfirmed; like-for-like comparison needed
On its HGX product page, NVIDIA projects that Rubin will deliver 10 times the token throughput of HGX B200. The comparison is based on "Kimi K2-Thinking," with time to first token of 500 milliseconds or less and 4,000 input and 4,000 output tokens. However, Rubin uses sparse NVFP4 while B200 uses dense NVFP4, so the computational conditions are not fully identical. The 10x figure should therefore be read as a projection comparing GPUs of different generations under specific conditions.
This performance projection also does not compare the same Rubin GPU before and after its HBM4 and NVLink bandwidth reached current values. It does not prove that lowering stated bandwidth has no effect on performance, and conversely, simply discounting the 10x projection by the 12.7% or 16.7% bandwidth differences would not yield actual processing performance. AI inference performance is determined by a combination of factors, including compute capability, memory access, GPU-to-GPU communication and software optimization.
To judge the effect of the specification changes accurately, the target GPU SKUs and final specifications for HGX and NVL72 must first be fixed. Measurements should then use the same AI model and numerical precision, with matched conditions such as batch size, input token count and generated token count. Comparing time to first token (TTFT) and token throughput during generation would show how actual inference performance differs. Measuring effective HBM4 bandwidth and GPU-to-GPU communication latency would further help isolate the causes of any difference.
At present, the exact timing of and reasons for NVIDIA's change to the stated bandwidth, as well as the final specifications of each SKU that will ship, have not been confirmed. What is clear is that the published NVL72 bandwidth is lower than in earlier official explanations, and that HGX still shows a discrepancy between single-GPU and eight-GPU specifications. If NVIDIA clarifies these specifications and measurements of inference performance on real hardware become available, it will be possible to judge how much the bandwidth differences affect actual AI workloads.