Panmnesia, a South Korean semiconductor IP startup, and a research team from Meta Platforms' infrastructure division (Meta Infra) announced on September 8, 2026, a next-generation AI infrastructure architecture that uses Compute Express Link (CXL) to tightly couple an entire data center as if it were a single massive semiconductor chip. The research was published as an invited Review in the British scientific journal Nature Reviews Electrical Engineering. This marks the first time a semiconductor startup has led a review article in the journal, and the first time the publication has featured a review addressing CXL and AI data center architecture.
The scale of frontier AI model training has ballooned to trillions of parameters. As a result, computing infrastructure now involves thousands of accelerators frequently exchanging terabytes of intermediate data. Because current distributed training relies on barrier synchronization—requiring every participating chip to stay in lockstep—a communication delay on even a single device can stall the progress of the entire system. Controlling variance in network latency (tail latency) while keeping the entire compute fleet operating as a single coherent execution environment has emerged as a structural challenge in scaling up models.
A "single-chip" data center concept that breaks down rack boundaries
The efficiency of distributed training does not automatically hold up as more computing resources are added. In one large-scale AI system measurement cited in the paper, increasing the number of participating chips sixfold caused per-device execution efficiency to drop to the mid-80% range. The cause was not insufficient compute performance but rather the rapid growth of data dependencies and synchronization waits. Production network measurements have reported cases where the 99th-percentile latency—close to the worst case—reaches roughly five times the median.
Conventional distributed systems have fixed CPUs, GPUs, and memory at the server level, connecting nodes via networks such as Ethernet or InfiniBand. But in AI training that relies on barrier synchronization, no matter how quickly individual accelerators finish their computations, every other chip is forced to wait until the transfer from the slowest node completes.
The "One-Chip-Like Datacenter" concept proposed by Panmnesia and Meta attempts to eliminate this latency uncertainty at both the physical and protocol layers. It discards the traditional server-based framework, treating the entire data center like the on-chip network (NoC) inside a processor, with hardware directly arbitrating cache coherence and memory sharing.
The structural limits of NVLink and scale-out RDMA
Understanding the significance of this proposal requires comparing it with the interconnect structures used in today's leading-edge AI clusters. In currently dominant configurations such as NVIDIA's GB200 and GB300 NVL72, the accelerators within a rack are interconnected at high speed via NVLink and NVLink-C2C, forming a tightly coupled scale-up domain.
The problem arises the moment communication has to leave the rack. In cross-rack, scale-out communication, data is sent through a NIC to an RDMA network (RoCE or InfiniBand), where it passes through multiple switch queues, routing decisions, and adjustments by the OS software stack. At this point, the data crosses three separate system boundaries: address space, transaction ordering, and fault-recovery management domains.
This two-tier structure causes the round-trip latency for a 256-byte inter-device access to jump into the microsecond range. Even if intra-rack NVLink communication completes in tens of nanoseconds, crossing a rack boundary degrades communication time by an order of magnitude or more, widening the variance in completion times.
By contrast, a CXL-based scale-up fabric places CPUs, accelerators, and memory within a single hardware-managed domain. CXL operates on top of the PCIe physical layer and supports I/O control (CXL.io), accelerator cache participation (CXL.cache), and direct memory load/store (CXL.mem). Rather than sending and receiving access to remote nodes as "network messages," this approach shifts to directly reading and writing data as part of a hardware-guaranteed memory hierarchy.
Three key hardware components behind sub-microsecond latency and 960-way coherence
The CXL specification itself only defines protocol agreements; depending on the internal hardware implementation, latency variance may not be sufficiently suppressed. The paper therefore defines three core hardware components needed to achieve predictable, low latency at data center scale.
First is a high-fan-out, non-blocking switch. By consolidating a large number of connection ports into a single stage, the number of switch hops is minimized, and a non-blocking structure prevents internal contention even when inputs converge simultaneously. This keeps packet path length and processing time consistent during communication patterns—such as All-Reduce or parameter exchange—where traffic surges from all devices at once.
Second is the Link Acceleration Unit (LAU). At the fabric boundary, it rapidly translates local addresses and metadata into a shared fabric-wide address space of up to 4 PB (petabytes). It also identifies a total of 26 transaction types—8 CXL.io, 6 CXL.cache, and 12 CXL.mem—and handles port assignment, retries, and congestion control. By moving this kind of protocol processing, previously handled by firmware, into a fixed hardware pipeline, the design eliminates latency fluctuations caused by control-software interrupts. Congestion control also kicks in immediately via hardware once queue occupancy reaches moderate (10%) or severe (25%) thresholds.
Third is the fabric controller. It splits and reassembles transactions into physical transfer units, centrally checking data integrity, retries, and transaction ordering. Across a large-scale fabric of up to 4,096 devices, it arbitrates so that all ports operate under the same priority policy.
データを表で見る
| Number of Accelerators (units) | |
|---|---|
| Conventional Reference Design (per CPU) | 2 |
| Proposed Design (per CPU) | 16 |
| Current NVL72 Domain | 72 |
| Proposed Coherence Domain | 960 |
Combining these hardware components dramatically expands the manageable system scale. In the conventional reference design, a single CPU managed only two accelerators; even under conservative CXL.cache assumptions, this expands eightfold to 16 accelerators per CPU. Furthermore, by having roughly 60 such CPU groups share the same address space and transaction ordering rules, up to 960 accelerators can operate within a single scale-up coherence domain.
Compared to the 72-accelerator scale-up domain offered by the current NVLink-based NVL72, 960 accelerators represent roughly 13.3 times the density. Round-trip latency for a 256-byte cross-rack access also drops sharply—from the microsecond range typical of scale-out RDMA networks to the sub-microsecond range enabled by fixed-hop CXL paths.
The 7-meter copper limit and the path toward optical CXL
However, this architecture cannot be deployed unconditionally across an entire data center. A severe physical constraint—signal loss that increases with transmission speed—stands in the way.
At the 128 GT/s transmission speeds targeted by PCIe 6.0/7.0 and CXL 4.0-generation standards, high-frequency signal attenuation and jitter over copper cabling become extremely severe. Even with two retimers inserted along the path, the physical limit for electrical signal transmission remains around 7 meters. Translated into standard server rack layouts, this corresponds to the limit of roughly 6 to 7 racks placed side by side that can be connected via copper.
This 7-meter figure assumes an ideal wiring environment and is not an unconditional guarantee. Signal margin is eroded by connector insertion/removal loss, trace length on printed circuit boards, retimer placement, and rising operating temperatures. Rack-internal wiring design also involves trade-offs: vertical routing shortens path length but obstructs cooling airflow, while horizontal routing preserves airflow but lengthens the wiring path. Physical implementation details—such as placing switch trays at the center of a rack to minimize variance in cable length—are themselves critical to the success of the latency architecture.
Extending scale-up domains beyond 7 meters requires adopting optical interconnect technologies such as CXL-over-Optics, optical backplanes, or Co-Packaged Optics (CPO). Converting to optical signals would allow the fabric to extend across an entire data center floor.
However, optical interconnects merely ease transmission-distance constraints—they do not solve practical challenges such as transaction ordering guarantees, cooling, packaging, supply chain availability, or total cost of ownership (TCO). In early deployments, a realistic approach would be a hybrid configuration that retains copper for short intra-rack wiring while gradually introducing optics for longer inter-rack or inter-row connections.
Fault recovery shifts focus from the server level to the device level
Beyond reducing latency, the One-Chip-Like Datacenter concept also changes how systems are maintained and recovered from failures.
In this architecture, physical resources are disaggregated at the "tray" level. Compute trays, memory trays, and switch trays are each separated into independent enclosures, which are then hierarchically bundled into "pods" and ultimately into a higher-level "fabric" built on multi-tier Clos or fat-tree topologies. While resource disaggregation in conventional data centers has largely aimed at eliminating the 50%-plus resource idling that occurs between independent servers, this design links disaggregation to eliminating synchronization waits and isolating faults.
In conventional server configurations, a hardware failure in any single component—motherboard, memory, or accelerator—required disconnecting an entire server from the cluster. As a result, other healthy CPUs and GPUs on that server were also taken offline, leaving compute resources idle. In a tray-disaggregated CXL environment, by contrast, it becomes possible to isolate only the individual failed device and hot-swap it while the system remains online.
Operating in multi-tenant environments requires a design that clearly separates management of the shared address space from the separation of access privileges. Maintaining cache coherence at the hardware level is not the same as granting different users or workloads permission to view each other's data. Encryption via CXL IDE (Integrity and Data Encryption) at the lower fabric layer, along with hardware access control at switches and endpoints, is essential.
Panmnesia, which made the announcement, has already completed silicon implementation and verification of its core IP—including the "PANSWITCH" ASIC switch chip, which supports both PCIe 6.4 and CXL 3.2—and is preparing for commercial supply. The concept of running a data center as a single computer has moved beyond the stage of laboratory simulation and into verification with real silicon and actual hardware. Going forward, the timing of mass adoption for optical CXL technology and the effectiveness of dynamic fault-recovery policies at large operating scale will be key checkpoints for evaluating infrastructure deployment.