Preferred Networks (PFN) and U.S.-based Tenstorrent announced on October 20, 2026 that their joint research on a generative AI processor using photonics-electronics convergence technology has been selected for a project run by the New Energy and Industrial Technology Development Organization (NEDO). PFN will develop an AI chiplet using 3D memory packaging technology, while Tenstorrent will develop a CPU chiplet that supports confidential computing. The two companies will integrate their technologies into a single system. Their goal is a computing platform that can handle generative AI training and inference with high performance and high power efficiency. Research and development will continue through fiscal 2031, with commercialization planned afterward. The key question is whether advances in individual semiconductor technologies can translate into better performance for the AI system as a whole.
Photonics-electronics convergence and 3D memory aim to ease AI processing bottlenecks
The AI chiplet PFN is developing is characterized by extremely high memory bandwidth, achieved through 3D memory packaging technology. A chiplet is a technique that divides a processor's functions among several smaller semiconductor chips and combines them to form a single system. In this joint research, the two companies will develop an AI compute chiplet and a CPU chiplet, then integrate them using photonics-electronics convergence technology and advanced packaging. By improving computation, memory access, and chip-to-chip communication, they aim to raise the performance and power efficiency of generative AI processing.
Generative AI performance depends on more than the raw computing power of the processing units. Large volumes of data must be supplied from memory to the compute units, so if data transfer cannot keep up, the available computing power cannot be fully used. Mynavi TECH+ explains that the 3D memory packaging is intended to place memory in a stacked arrangement, shortening the distance to the processor, securing the necessary transfer bandwidth, and making data movement more efficient. The idea is to raise overall system efficiency by improving how data is supplied to the compute units, not just the performance of the units themselves.
Photonics-electronics convergence, meanwhile, combines electrical and optical signals to speed up data communication between processors and other components while reducing power consumption. With conventional electrical wiring, bandwidth and power consumption become problems as the volume of transferred data grows. By using light for part of the data communication, the researchers aim to transmit large volumes of data more efficiently. While 3D memory packaging mainly improves data transfer between the compute units and memory, photonics-electronics convergence handles communication between processors and similar components. In this joint research, these technologies will be combined with advanced packaging to improve data transfer efficiency across the whole system.
The development content and division of roles announced by PFN can be summarized as follows:
| Development target | Responsible party | Main development content |
|---|---|---|
| AI chiplet | PFN | Aim for extremely high memory bandwidth through 3D memory packaging that applies advanced processes |
| CPU chiplet | Tenstorrent | Develop a CPU that supports confidential computing, using advanced processes and open architecture |
| System integration | PFN and Tenstorrent | Integrate the AI processor into a single system using photonics-electronics convergence and advanced packaging |
This division of roles shows that work to expand the AI chiplet's memory bandwidth and work to improve the performance of the whole system, including the CPU, will proceed in parallel. However, even if the AI chiplet achieves high performance on its own, that does not necessarily carry over directly to the processing speed or power efficiency of the whole system. Coordination with the CPU, chip-to-chip communication, and the data transfers that occur in real AI applications can also affect performance. The higher performance and efficiency the companies are seeking in training and inference will need to be verified on the integrated system.
Support for confidential computing is also an important development item for the CPU chiplet Tenstorrent is handling. Confidential computing is a technology intended to protect data not only when it is stored or transmitted, but also while it is being processed. Mynavi TECH+ points to its relevance for uses that handle highly sensitive data on cloud or shared AI infrastructure. However, adopting an open architecture for the CPU design is a separate matter from ensuring the security of confidential computing. In this research, the plan is to develop the CPU chiplet and verify its confidential computing support through demonstration software.
R&D runs through fiscal 2031, with commercialization to follow
This joint research will be carried out as part of NEDO's R&D project to strengthen the foundations of post-5G information and communication systems. In the notice of selection NEDO published on October 20, the project period is set at, in principle, within five years (60 months) from the start. PFN, for its part, said it will continue the joint research through fiscal 2031 and aim for commercialization afterward. In other words, fiscal 2031 is a target year for R&D, and it has not been decided that a product will go on sale by then. Because NEDO's condition of "within 60 months of the start of R&D" and PFN's plan of "through fiscal 2031" are expressed differently, the research start date also cannot be simply worked out backward from the announcement date.
The timeline also needs to be distinguished from PFN's separate AI processor development plans. ITmedia AI+ reported on October 21 that the planned availability of PFN's existing product plan, the "MN-Core L1000," has been changed from 2026 to 2027. However, PFN's announcement does not state that the AI chiplet to be developed in this joint research is the MN-Core L1000 itself. The availability timing of the MN-Core L1000 and the completion of the joint research running through fiscal 2031 therefore cannot be equated. They should be regarded as separate development plans.
Through this project, NEDO aims to secure a technology base that allows advanced semiconductors supporting future post-5G information and communication systems to be designed and manufactured in Japan. As demand for computing resources grows with the spread of generative AI, technology development covering memory and communication, not just semiconductor computing performance, has become important. However, the phrase "cutting-edge process" in the PFN and Tenstorrent announcement does not reveal the specific manufacturing process to be used or the manufacturing partner. The policy goal of securing advanced semiconductor technology in Japan and the actual manufacturing location of the chiplets to be developed need to be considered separately.
Practical performance to be tested with AI for Science and physical AI
In addition to PFN and Tenstorrent, several universities and research institutions will take part in the joint research. The University of Tokyo, Kobe University, and Toyo University, as subcontractors, will be responsible for R&D on applications optimized for specific fields, aimed at "AI for Science," which applies AI to scientific research, and "physical AI," which perceives, decides, and acts in the real world. The Japan Agency for Marine-Earth Science and Technology (JAMSTEC) and the Japan Atomic Energy Agency (JAEA) will also participate as subcontractors. Tenstorrent Japan is scheduled to handle the design of the CPU chiplet and the development of software to verify the confidential computing functions.
A distinctive feature is that the research covers not only the development of the semiconductors themselves but also the AI applications that will actually use them. Even if a processor's computing performance and memory bandwidth improve, the expected benefits will not materialize unless real applications can make full use of that performance. Evaluating the results of this research will require checking not only the AI chiplet's memory bandwidth but also the power consumption of the whole system, including optical connections, and the processing performance of the target applications. For confidential computing as well, verification using demonstration software will examine what data can be protected and to what extent. These are evaluation items that can be inferred from the announced division of development roles; they do not mean that each institution has already demonstrated performance or security.
The high-performance, high-efficiency AI processor that PFN and Tenstorrent are aiming for is, at this point, a goal of the joint research. The announcement does not give specifics such as the memory bandwidth or power consumption of the system to be developed, or how much faster it would be than existing products. To evaluate the research results going forward, it will matter what system configuration was used, which AI applications were run, and under what conditions performance and power consumption were measured. In particular, AI for scientific research and physical AI may demand different processing performance, response speed, and power efficiency, so verification tailored to each use will be needed.
What to watch in the research ahead is how much performance improvement and power reduction 3D memory packaging and photonics-electronics convergence deliver in actual AI processing. Once the target applications and measurement conditions become concrete, it will be possible to assess which processing bottlenecks the expanded memory bandwidth and the introduction of optical communication resolve. Whether the advances in individual semiconductor technologies can be turned into better performance for the whole system, and that effect demonstrated on real AI applications, will be an important factor in judging whether the results can be commercialized.