HBM has a structure in which multiple DRAM dies are stacked vertically, and increasing the number of stacked layers is the primary means of packing more memory capacity into a limited height. However, the thinner the dies become, the more prone they are to warping and misalignment, and SK hynix, Samsung, and Micron have yet to align on the timing of mass production and the bonding method for 16-layer (16-Hi) products. Against this backdrop, a research team at POSTECH (Pohang University of Science and Technology) in Korea has announced a new bonding technology that stably stacks more than 10 layers of ultra-thin silicon chips roughly 14 micrometers thick. By integrating transfer printing and metal bonding into a single process, the team says it achieved roughly 4x the density at the same height as an existing 12-layer HBM structure. However, what was stacked were test chips equipped with TSVs and redistribution layers but without DRAM circuitry, and a demonstration of integration into an actual HBM memory device has not yet been shown.
A Bonding Process That Achieves Stable Stacking of 10+ Layers in a Single Step
A research team led by Professor Kim Seok of POSTECH's Department of Mechanical Engineering announced on June 30, 2026, a new bonding process that stably stacks more than 10 layers of ultra-thin silicon chips approximately 14 micrometers thick. The research was carried out jointly with integrated-program student Uhyeon Kim and Dr. Hohyun Keum of the Korea Institute of Industrial Technology (KITECH). The results were published online in the academic journal Results in Engineering (published by Elsevier/ScienceDirect), with the DOI 10.1016/j.rineng.2026.111194. Funding for the research was provided by, among others, the National Research Foundation of Korea (NRF)'s "PIM AI Semiconductor Core Technology Development Project."
The team integrated "transfer printing," which completes chip movement, bonding, and electrical connection in a single process, with "real-time bonding," simultaneously advancing Cu-Sn diffusion bonding—in which copper and tin react—under low-temperature, low-pressure conditions of 180°C or below and 20kPa or below. The research team explains that these conditions minimized alignment errors and warping between layers. They calculate that, when fitted into a package of the same height, this would allow roughly 4x as many chips to be stacked compared with an existing 12-layer (12-Hi) HBM structure. This "4x" figure is strictly a comparison at the same package height, and does not mean that performance itself is quadrupled.
Overseas technology trade media have also reported that this bonding process minimized mechanical strain across the entire stack of more than 10 layers and maintained precise alignment between layers. However, the paper itself, published on ScienceDirect, could not be directly accessed due to restrictions on automated crawling tools, so this article has not been able to confirm specific figures for alignment error or bond strength.
How Transfer Printing and Real-Time Bonding Changed the Order of Bonding Operations
There are currently two main bonding methods used in mass-produced HBM. MR-MUF (Mass Reflow Molded Underfill), adopted by SK hynix, bonds dies connected via through-silicon vias (TSVs) all at once through reflow (solder melting), then fills the gaps with a molding resin. TC-NCF (Thermal Compression Non-Conductive Film), adopted by Samsung, sandwiches an insulating film between dies and press-bonds them by applying heat and pressure. Both companies are currently reconsidering the timing of their transition to hybrid bonding—which directly bonds metal pads and insulating films without a layer of solder or resin in between—for next-generation HBM4E and beyond.
With transfer printing, an ultra-thin chip is moved to its target position while electrical connection via Cu-Sn diffusion bonding is completed simultaneously. According to the research team, combining alignment and bonding into a single action reduces the room for errors to accumulate across processes, making it possible to stack more than 10 layers while suppressing warping even with dies as thin as 14 micrometers.
Hybrid bonding often requires highly precise planarization and heat treatment on the order of several hundred degrees, and TC-NCF also subjects dies to thermal stress during the thermal compression process. MR-MUF, too, can generate thermal shock to the dies due to rapid heating during reflow. The low-temperature, low-pressure conditions of 180°C or below and 20kPa or below adopted by POSTECH address the constraint that thinner dies are more prone to warping from heat and pressure, with the low bonding temperature playing a key role here. The team is responding, from a different angle, to an industry-wide challenge in which pursuing thinner dies increasingly makes reconsidering the bonding method unavoidable.
What a 14-Micrometer Thickness Poses to the HBM4 Mass-Production Benchmark
Under the JEDEC standard, HBM4's overall stack height is set at 775 micrometers. According to industry explainer articles, achieving 16 layers within this envelope requires thinning each DRAM die from the conventional approximately 50 micrometers down to about 30 micrometers, according to industry estimates. The 14 micrometers demonstrated by POSTECH is less than half of this mass-production target. Looking at the numbers alone, the laboratory achievement already far exceeds the thinness the industry is aiming for.
HBM4's figure of 30 micrometers refers to the thickness of a finished die that incorporates the DRAM cell array and control circuitry. What POSTECH stacked, on the other hand, are silicon chips containing only vertical wiring structures and horizontal wiring, with no circuitry that functions as memory included. Even if, by the single metric of thinness alone, it appears to exceed the mass-production target, the things being compared are fundamentally different.
The number of HBM layers has increased with each generation. The first generation in 2013 had 4 layers (4-Hi), and the second generation in 2016 had 8 layers (8-Hi). HBM3, standardized in 2022, supported 4, 8, and 12 layers, with 16 layers remaining only a specification for future expansion. 16-layer HBM3E was announced by SK hynix in November 2024, and HBM4, whose JEDEC standard was established in April 2025, aims for 16 layers (16-Hi) alongside the start of mass production in 2026.
While the number of stacked layers has quadrupled over the past decade or so, both HBM3 (from standard publication in January 2022 to mass-production start in June of the same year) and HBM4 (from standard publication in April 2025 to mass-production start in 2026) transitioned in less than a year, in each case premised on existing bonding methods. If POSTECH's technology is to join this history, it will likely be not as a record for thinness, but as an entry point through which a new bonding method with no mass-production track record accumulates yield and reliability data.
The Race Among SK hynix, Samsung, and Micron for 16-Layer HBM4 Mass Production, and Where POSTECH Stands
NVIDIA is reportedly requesting that SK hynix, Samsung, and Micron supply 16-layer (16-Hi) HBM4 by the fourth quarter of 2026 in order to secure the memory capacity needed for its AI-focused GPUs. NVIDIA CEO Jensen Huang revealed in June 2026 that all three companies had passed HBM4 product qualification and entered the mass-production stage. Specific supply volumes for 16-layer products have not been disclosed, but approaches to mass production differ. SK hynix is pursuing 16-layer production using the conventional MR-MUF method, while both Samsung and SK hynix are reconsidering the timing of adopting next-generation hybrid bonding, with reports suggesting that 16-layer HBM4E will be the first candidate for its adoption.
Whereas the competition between SK hynix and Samsung is a contest over layer count—"how to stack dies of the same thickness"—what POSTECH is pursuing is a different axis of efficiency: "how many thinner dies can fit within the same height." The two are less competing technologies than different questions being pursued. No publicly announced adoption plans by companies for POSTECH's transfer printing plus real-time bonding method can be confirmed at this time. If this bonding method were to be adopted by mass-production manufacturers, it could offer an advantage in manufacturing cost and stacking efficiency, while manufacturers that have invested in existing MR-MUF or TC-NCF lines could face the burden of switching equipment. This framing of competing interests is a hypothesis derived from industry structure, and information confirming joint research or technology transfer with any company cannot be verified at this time.
The Gap Remaining Before Mass Production, and the Next Applications Envisioned by Professor Kim Seok and Dr. Hohyun Keum
This announcement did not present specific yield figures, a demonstration of integration into an actual memory device, a timeline outlook for mass production, the status of patent applications, or whether there is joint research or technology transfer with any company. What the research team disclosed was strictly the demonstration results of the bonding process itself—transfer printing and real-time bonding—and the subsequent steps toward mass production are not included in the scope of this announcement. A gap that has not yet been closed remains between the significance of this as a research achievement and its practicality as a mass-production technology.
With that gap in mind, the research team speaks to the significance of the technology. Professor Kim Seok said, "Having achieved roughly 4x higher integration density compared with existing HBM, we hope this will be utilized as a core foundational technology for developing high-performance AI semiconductors and next-generation memory systems." Dr. Hohyun Keum said, "This micrometer-level ultra-precision alignment and bonding technology could also be widely applied to next-generation semiconductor and display manufacturing fields."
The technology of precisely stacking thin chips at low temperature and low pressure is commonly required not only in "chiplet" packaging, which combines multiple functional chips into a single package, but also in next-generation micro-LED displays. As the two researchers' comments suggest, the applications of this technology are not limited to HBM. It is also conceivable that the technology is technically continuous with fields handled by Japanese semiconductor manufacturing equipment makers, such as DISCO Corporation, which has a global presence in ultra-thin wafer grinding and dicing equipment, and Tokyo Electron, which handles deposition and bonding equipment.
The figure of 14 micrometers already falls below the thinness target that HBM4 aims for in mass production. As Professor Kim and Dr. Keum note, the significance of this bonding technology is not confined to a single application in HBM. The remaining challenge for this technology to move from basic research to a mass-production technology has shifted from the pursuit of thinness to proving reproducibility through operational demonstration in an actual device incorporating DRAM circuitry and through yield data.