PsiQuantum and AMD announced on November 12, 2026 an expanded partnership to co-design the computing infrastructure for fault-tolerant quantum computers. AMD plans to invest in PsiQuantum, though the amount has not been disclosed. Two days before the announcement, 15 researchers from the two companies posted a paper to arXiv reporting a design that runs the decoder, the process that estimates where errors occurred in photonic error correction, on AMD FPGAs (semiconductors whose circuits can be reconfigured). The press release cites this paper. The paper reports that decoding latency for a distance-8 block is 10.11 microseconds in a 250 MHz implementation of the full network. The paper's target is 10 microseconds. The 6.59 microseconds highlighted in the abstract is a value under a different condition, and you have to look at that condition to judge how close the paper's numbers come to the required speed.
AMD's Investment Is Planned; the Partnership Extends From FPGAs to GPUs and CPUs
According to the companies' announcement, the partnership started with the AMD Versal FPGAs that PsiQuantum chose for developing its fault-tolerant platform. The expansion adds AMD Instinct GPUs, AMD EPYC CPUs, and the ROCm software stack, while PsiQuantum provides its silicon photonics foundation (a technology that builds optical circuits using silicon semiconductor manufacturing). The goals are the computing infrastructure needed to run utility-scale fault-tolerant quantum computers, and co-design of hybrid applications that combine quantum computing, HPC (high-performance computing), and AI. AMD CTO Mark Papermaster said that building large-scale quantum systems requires leadership in classical computing as well.
Funding and site plans are still at the planning or consideration stage. According to Reuters, AMD plans to invest in PsiQuantum, and the companies have not disclosed an amount. The two companies say they will "consider" establishing a presence at the Illinois Quantum and Microelectronics Park (IQMP). PsiQuantum is the park's anchor tenant, and the park broke ground on September 30, 2025.
On September 10, 2025, PsiQuantum raised $1 billion in a Series E at a $7 billion valuation, with NVIDIA's NVentures also participating. CEO Victor Peng is a former AMD president and former CEO of Xilinx, the FPGA company AMD acquired. According to PsiQuantum's announcement, he became interim CEO on February 10, 2026, and was the permanent CEO by the time of the July 15 announcement.
The first application areas named are pharmaceutical research and drug discovery. The companies say PsiQuantum's computational chemistry methods are already running on AMD hardware and have produced early results in simulating covalent inhibitors relevant to oncology drug discovery. No figures or comparison baselines are given for these results. The release also says the partnership aligns with the U.S. Department of Energy's (DOE) Quantum Genesis Priority Applications (QGPA). According to the DOE page, the eight priority applications span four areas including chemistry and materials, and DOE is also watching emerging applications such as plasma physics, biochemistry, and optimization (published October 8, 2026).
The release says PsiQuantum researchers worked with AMD to optimize PRISM, a high-accuracy machine-learning decoder, for low-latency implementation on programmable hardware accelerators, and links to the paper. The companies describe the design as real-time error correction for utility-scale photonic quantum computing that balances speed and accuracy. The paper is the place where the partnership's technical claims can be checked against numbers. It is a non-peer-reviewed preprint; of its 15 authors, nine are affiliated with PsiQuantum and six with AMD.
In Photonic Error Correction, Decoder Delays Slow the Logical Clock
In fault-tolerant quantum computing, classical processing must infer where errors occurred from qubit measurement results (the syndrome). This is the decoder. If the decoder falls behind the quantum side, feedforward operations (processing in which the next operation is chosen based on earlier measurement results), such as injecting magic states (special quantum states used for some operations), must wait for its output, and the logical clock slows. Decoder speed directly affects how fast the computation proceeds.
In PsiQuantum's photonic approach, erasure errors are among the dominant error types. Fusion-based quantum computing is a photonic method that advances computation by joining small entangled states through measurements (fusions), and photon loss and probabilistic fusion measurements produce erasure errors. An erasure error is one where the location of the lost qubit information is known. PRISM is a Transformer-based machine-learning decoder developed by PsiQuantum and AMD researchers, and it uses this location information as input.
According to the paper, PRISM was evaluated up to distance 24 on fault-tolerant protocols based on surface codes, color codes, and quantum LDPC (low-density parity-check) codes. Distance is a measure of an error-correcting code's size; larger values tolerate more errors. The authors report that it achieves logical error rates (the rate of errors remaining after error correction) comparable to integer linear programming (ILP)-based decoders in far less time. This equivalence is described as holding under conditions that include error rates up to 50% of the threshold.
However, this equivalence is a result for the pre-quantization PRISM. What was loaded onto the FPGA is a different, quantized version.
The Abstract's 6.59 Microseconds Is a 400 MHz Estimate; the Full Implementation Gives 10.11 Microseconds
The paper set its FPGA implementation target at 10 microseconds per distance-8 linked-loopy-diamond (LLD) periodic block. LLD is the name of a type of fusion network the paper used for evaluation. The paper explains that it adopted this target because the scale fits interleaved photonic architectures, where, assuming a physical clock of 1 GHz or higher, the logical cycle time can be tuned between 1 nanosecond and 10 microseconds. Decoding a distance-8 block roughly corresponds to decoding eight rounds of a distance-8 surface code.
The implementation target is the AMD Versal Premium VP1902. AMD announced it on June 27, 2023 as an adaptive SoC for emulation and prototyping, and AMD describes it, by its own comparison, as the world's largest FPGA-based SoC. It has 18.5 million logic cells, and according to the paper 8,460,288 LUTs (the basic logic elements of an FPGA). The model loaded is the quantized Q-PRISM, with model dimension dM of 32 and a parallelism configuration of [5,1]. The values in the paper's Table II are as follows.
| Clock frequency | How it was verified | Cycles | Latency | Average decoding time per block |
|---|---|---|---|---|
| 250 MHz | Full network implemented | 2,528 | 10.11 microseconds | 2.39 microseconds |
| 400 MHz | Achievement confirmed by implementing one message-passing layer and one perceiver layer that make up the model | 2,636 (108 additional cycles) | 6.59 microseconds | 1.56 microseconds |
Against the paper's 10-microsecond target, decoding a distance-8 LLD block took 10.11 microseconds at 250 MHz with the full network implemented, and 6.59 microseconds at 400 MHz as estimated from single-layer implementations. The 10.11 microseconds is 0.11 microseconds longer than the target, and 6.59 microseconds is shorter than the target.
The latter, however, is not a value confirmed with the full network implemented. The abstract and conclusion highlight 6.59 microseconds, but the 400 MHz operation was shown on a layer-by-layer basis, and a full 400 MHz implementation is left as future work. The paper says that, given the pipeline design and the VP1902's resources, the frequency of the whole network can be predicted well enough from the frequencies of its components.
Latency is the time from the first input of a block to completion of its output, including input loading. In real-time operation the syndrome arrives sequentially, so the paper notes that this value could shrink further. The average decoding time per block is the average time one block takes when blocks are processed back to back. The column to compare with the 10-microsecond target is latency.
The paper obtains cycle counts from RTL (design-level descriptions of circuit behavior) timeline measurements, and frequencies from placement and timing checks on the FPGA in AMD's design tool Vivado 2026.1. Time is cycles divided by frequency: 10.11 microseconds is 2,528 cycles at 250 MHz, and 6.59 microseconds is 2,636 cycles at 400 MHz. Raising the frequency adds 108 cycles to meet timing, but the shorter cycle outweighs this and total time shrinks.
The FPGA Runs a 2-Bit Quantized Version; the Paper Describes Its Accuracy in Two Ways
Quantization represents weights and computations with fewer bits. It makes circuits smaller and faster, but accuracy can drop. The FPGA model uses 2-bit weights and activations, with ternary weights. It is built with quantization-aware training, which trains the model assuming low-bit-precision operation so the accuracy loss is accounted for. PRISM was trained on AMD Instinct MI350X GPUs.
The paper states that the quantized model is less accurate than the reference decoder in Figure 3, while also stating that the logical error rate of the model obtained by quantization-aware training is comparable to that of the pre-quantization model. Appendix D notes that the experiment in which the logical error rates before and after quantization were similar used different training settings, so it is not a comparison that isolates the accuracy loss from quantization. The equivalence with ILP in the previous section is a result for the pre-quantization PRISM, while 10.11 and 6.59 microseconds are values for the quantized version. Accuracy and speed cannot be read side by side as the performance of one and the same model.
The paper also gives estimates for configurations with higher parallelism. With a [24,5] configuration, it estimates 3.39 to 4.99 microseconds at dM=16 and 3.5 to 5.16 microseconds at dM=32. The dM=16 case assumes model improvements that achieve sufficient logical error rates, and the dM=32 case assumes a future FPGA with greater capacity. Neither is an implemented value; they are estimates and cannot be placed on the same footing as 10.11 microseconds.
Open Points: a Full 400 MHz Implementation and Larger Distances
There are two points to check in reading the gap to the target. One is the full 400 MHz implementation. The paper says the whole network can be predicted from component frequencies, but leaves full placement for future work. The other is the accuracy of the quantized version. The Appendix D comparison does not isolate the effect of quantization alone, so the accuracy of the 2-bit version that produced 10.11 and 6.59 microseconds cannot be read from it.
The companies plan to give more details about the partnership at SC26, held in Chicago November 15–20.
The authors expect that latency under 10 microseconds is possible even at the larger distances needed at utility scale, citing decoder structure, quantization, and hardware improvements as means. However, the FPGA implementation covers only distance 8, and the paper does not show an implementation at larger distances.