On November 2, 2026, Qualcomm announced that tests on early silicon of its next-generation memory technology, High Bandwidth Compute (HBC), have confirmed that memory reads, writes and near-memory compute work. The technology performs computation right next to the memory to cut the power needed to move data, and it has now moved from the design stage to testing on real hardware. The Dragonfly AI250, an AI inference accelerator that will use HBC, is scheduled to begin sampling in the first half of 2027. Qualcomm estimates that HBC can deliver more than five times the bandwidth per watt of HBM4, but that figure is a conversion of early-silicon measurements to target operating conditions, not performance confirmed on a finished product.
HBC computes near memory, and early silicon shows it working
HBC stacks LPDDR-class DRAM on top of a compute die and processes data close to the memory. With conventional HBM, large volumes of data must be transferred from the stacked DRAM to an external compute processor. HBC instead runs bandwidth-hungry operations inside the stack and passes only the results to the external processor, reducing the amount of data that moves. In a technical explainer published in July 2026, Qualcomm described frequent data movement between memory and compute units as a key constraint on AI inference performance and power efficiency.
A key point in this design is the distinction between the external interface's transfer rate and "effective memory bandwidth." Because HBC computes using the wide internal bandwidth of the memory, it can achieve high data-processing throughput even when little data is sent out. HBC's effective memory bandwidth is therefore not the same thing as the physical transfer bandwidth of the connection between the memory and an external processor.
Qualcomm ran the validation at its San Diego research facility using industry-standard automated test equipment. It says it fed in randomly generated model weights and activations, at data sizes intended to reflect real products, and performed memory reads, writes and near-memory compute. Weights are the parameters an AI model holds, and activations are the data generated during computation. The validation confirmed that HBC's main data paths function on actual silicon.
However, this was not a test that ran a finished large language model and measured response-generation speed. It was a functional check of the circuitry using random data, and should be distinguished from inference benchmarks on a finished product or performance comparisons by third parties.
What the "5x-plus" power efficiency over HBM4 and 133TB/s mean
According to ServeTheHome's report, Qualcomm says the results show more than five times the bandwidth per watt of HBM4's published specifications, and 18 times the bandwidth of external LPDDR5X. The former is bandwidth per watt of power consumed, while the latter is a comparison of bandwidth itself, so the metrics differ. Neither means AI inference would run five or 18 times faster.
The official Qualcomm announcement also includes an important note on how the comparison figures were derived. They are Qualcomm's own estimates, made by normalizing results measured on early silicon to target operating conditions and comparing them with competitors' published specifications. They are not the result of a direct, same-environment comparison of finished products using HBC and HBM4. The detailed conditions used for normalization and the absolute bandwidth values measured have not been disclosed, and final performance may vary with product configuration and the AI model being run.
The "133TB/s" figure Qualcomm announced in June 2026 is likewise not a value measured on this early silicon. It is a design target for the effective memory bandwidth of the entire AI250 card, described at the time as 18 times that of the AI200, which uses LPDDR5X. It has not been confirmed that this matches the "18x" comparison with external LPDDR5X in November in terms of subject or evaluation conditions.
The main figures and their status are summarized below.
| Announced | Figure / schedule | Comparison / scope | Status |
|---|---|---|---|
| November 2026 | 5x+ bandwidth per watt | HBM4 published specs | Qualcomm estimate from early-silicon measurements, normalized |
| November 2026 | 18x bandwidth | External LPDDR5X | Comparison based on early validation; absolute bandwidth not disclosed |
| June 2026 | 133TB/s effective memory bandwidth, 18x | Card-level comparison with AI200, which uses LPDDR5X | AI250 design target |
| June 2026 | 6x bandwidth per watt | Competing HBM published specs, normalized to card level | Design-stage estimate |
| Announced November 2026 | First half of 2027 | Dragonfly AI250 with HBC | Planned sampling |
Sources: compiled from Qualcomm's June 2026 product roadmap, July technical explainer and November validation announcement, and ServeTheHome's reporting.
These numbers represent, respectively, estimates based on early-silicon validation, design targets for a finished card, and a product development schedule. In particular, the "more than 5x vs. HBM4" figure cannot be treated as an achievement rate against the earlier 6x target, because it has not been confirmed that the comparison targets and normalization conditions are the same.
From a two-layer DRAM prototype to four layers: thermals and yield are open issues
According to ServeTheHome, the HBC prototype stack validated this time used two layers of DRAM, while Qualcomm plans a four-layer configuration for shipping products. The test results therefore may not carry over unchanged to the production version. A particularly important question is how to handle the heat generated by the compute die placed beneath the memory.
HBC reduces data transfer by placing the compute die right next to the DRAM, but the heat from that computation could affect the temperature of the stacked memory. Qualcomm says it also tested thermal behavior, but it has not disclosed specific temperatures or cooling conditions. Heat distribution when the stack grows from two to four layers, and stability during prolonged high-load operation, will be important items to confirm.
On the manufacturing side, Qualcomm has built redundancy and remapping mechanisms into the design to cope with memory defects. The design limits the impact on operation by substituting other memory regions for defective ones. The company also says it has put in place test methods to detect electrical problems, thermal issues, and failures in die-to-die bonds and interfaces. Qualcomm says it has already completed the tape-out of its data center products and has obtained working parts in initial bring-up of logic bonded with DRAM.
No specific figures on manufacturing yield or volume production capacity were given. A working early silicon is not the same as being able to mass-produce at stable quality. For HBC in particular, which stacks DRAM and compute dies, the precision of the bonding process and the handling of defects will affect manufacturing cost.
On the other hand, HBC may also lower packaging costs. ServeTheHome analyzes that if processing is done inside the stacked memory and less data is sent out, relatively inexpensive technologies such as conventional 2D organic substrates might be usable to connect the compute die to the external processor. HBM uses advanced packaging such as CoWoS and EMIB to link memory and compute processors at high bandwidth, and HBC may leave room to simplify that part.
Still, the process of stacking DRAM and bonding it to the compute die does not go away. Even if external connections are simplified, cost reductions for the product as a whole will not materialize unless the manufacturing quality and yield of the stacked portion can be secured.
The AI250 in the first half of 2027 will test real inference performance
Qualcomm plans to begin sampling the Dragonfly AI250, which uses HBC, in the first half of 2027. The AI250 will be part of the Dragonfly Rack, the company's data center platform for AI inference. However, what was disclosed is the timing for evaluation samples, not a general release or the start of volume production. The June 2026 announcement had indicated a plan for mid-2027, but the current wording alone does not allow us to conclude that the development schedule has been moved up.
To judge HBC's practical value, it will be necessary to confirm not just memory bandwidth but how much performance and power efficiency it achieves in real AI inference. Qualcomm itself acknowledges, in its comparative analysis of memory approaches, that HBC is not necessarily optimal under all conditions. For example, in the feed-forward network (FFN) layers of AI models with small batch sizes and strict latency requirements, SRAM built into the compute chip can in some cases match or exceed HBC's energy efficiency.
Evaluating the AI250 will therefore require comparing token generation speed and power consumption with the models, batch sizes and allowable latency held constant. Heat generation and cooling conditions in the four-layer DRAM configuration, stability over long runs and manufacturing yield will also influence data center adoption.
This validation moves Qualcomm's HBC from a design concept to a stage where its main functions work on real silicon. But it is still unknown whether the advantage of more than 5x bandwidth per watt over HBM4 will be reproduced in a finished AI accelerator. The AI250 sampling planned for the first half of 2027 will be an important opportunity to see whether HBC's approach of reducing data movement translates into better real-world AI inference performance and operating costs.