Samsung Electronics has moved to recruit experienced professionals spanning high-bandwidth memory (HBM) design, packaging, reliability evaluation, and customer technical support. According to Seoul Economic Daily, the recruitment period runs from July 13 to 27, 2026, covering six HBM-related job categories. The hiring comes right after Samsung began mass shipments of HBM4 in February and sent HBM4E samples to customers in May. Overlaying the job composition with the official roadmap reveals an aim to run HBM4 production ramp-up, HBM4E qualification, and HBM5 technology development simultaneously, shrinking the wait time between processes.
HBM is not a component completed simply by stacking fast DRAM. Core dies and logic base dies must be designed, thin dies stacked and bonded, heat and lifespan verified, and the product must then pass qualification on the customer's AI accelerator. This recruitment drive covers that entire chain from end to end. Lining up the job categories reveals where Samsung sees the risk of losing time.
The Six Job Categories Mirror the HBM Process Chart in Reverse
Of the six job categories reported by Seoul Economic Daily, the Memory Business Division is recruiting for five areas: core/base die design (both), reliability evaluation, package development, and application engineering. The Semiconductor R&D Center is separately seeking developers for next-generation HBM packaging processes. While the number of hires has not been disclosed, the scope of recruitment leaves no gap from the entry point of product development through to customer adoption.
| Job Category | Process Covered | Time to Shorten / Risk to Contain |
|---|---|---|
| HBM Core Die Design | DRAM analog/digital circuits, power delivery network | Balancing higher speed with low-voltage operation |
| HBM Base Die Design | Physical design, timing optimization, GPU interconnect | Handling 2,048 I/O pins and customer-specific specifications |
| HBM Reliability Evaluation | Lifespan of stacked dies, thermal stability, failure analysis | Detecting defects under high-temperature, high-load conditions |
| HBM Package Development | Bumps, TSVs, bonding, stacked structure | Improving thickness, thermal resistance, and mass-production yield |
| HBM Application Engineering | Evaluation on AI accelerators, customer qualification | Shortening the loop from sample to adoption |
| Next-Generation HBM Packaging Process | Hybrid copper bonding, TSV modules, copper pad planarization | Bonding precision and manufacturability for 16+ layers |
What stands out in this lineup is that back-end processes and customer support are given the same weight as circuit design. In HBM, improving one process shifts the burden onto another. Increasing I/O count to raise speed increases the base die's power consumption and heat generation; increasing the number of stacked layers tightens the requirements on bonding precision and thermal pathways. If a problem is found in the customer's environment, it must be traced back to design or process for a fix. Reducing that back-and-forth is better served by experienced professionals who connect processes than by simply adding headcount to each individual process.
The Seam Between 1c DRAM and the 4nm Base Die
HBM4, now in mass production, well illustrates the technical reasons behind this recruitment drive. Samsung uses its 1c—a 10nm-class 6th-generation DRAM process—for the core die, and its own Foundry's 4nm logic process for the base die. The I/O count doubled from HBM3E's 1,024 pins to 2,048 pins. Stable operating speed reaches 11.7Gbps per pin, with a maximum of 13Gbps, giving a single-stack bandwidth of up to 3.3TB/s.
When I/O count doubles, the base die can no longer simply serve as a passive pedestal that routes signals through. It must fit 2,048 lines of wiring into a limited area, align timing, and deliver power stably. Moreover, from HBM4 onward, the industry is moving toward Custom HBM, which tailors interfaces and control to match the design of GPUs or proprietary AI accelerators. This is why Samsung is recruiting for core die design and base die design simultaneously.
Samsung touts DTCO (Design Technology Co-Optimization)—jointly optimizing design and process by holding both Memory and Foundry in-house—as one of its strengths. However, having such an organization is not the same as producing good units within a short timeframe. In its Q1 2026 earnings call, the Foundry Business Division also laid out plans to maximize advanced-node utilization in Q2 and improve profitability through increased supply of HBM4 base dies. This recruitment of base die talent signals that Samsung is entering a phase where HBM is no longer treated as a product of the Memory Business Division alone, but is run in unison with Foundry's mass-production capacity.
This coordination is directly tied to sales plans as well. Samsung expects its 2026 HBM revenue to more than triple compared to 2025, and it is expanding HBM4 production capacity. Even leading in the speed race means nothing for revenue unless good core dies and base dies can be matched, stacked, and delivered to customers on schedule. What's needed during a mass-production ramp-up is not the fastest prototype, but the ability to stabilize yields across multiple processes at once.
With HBM4E, Heat and Stacking Become the Next Bottleneck
HBM4E, whose customer sample shipments began on May 29, packs 48GB into 12 layers. Its stable operating speed is 14Gbps, with a maximum of 16Gbps, giving a bandwidth of 3.6TB/s per single stack at 14Gbps. Samsung states this can be extended up to 4TB/s at maximum operation. While using the same combination of 1c DRAM and 4nm base die as HBM4, the company says it has improved power efficiency by 16% and thermal resistance characteristics by more than 14%.
The higher these figures climb, the more heat becomes a problem that can't be pushed outside the design. The Heat Path Block (HPB) that Samsung unveiled at COMPUTEX 2026 adds a pathway to dissipate heat near the D2D PHY within the base die, which handles high-speed communication between the GPU and HBM. It is currently being validated with HBM4E, with plans to apply it starting from HBM5. Because this involves embedding a heat-dissipation pathway near the heat source into the package interior, it requires jointly adjusting circuitry, materials, bonding, and mechanical strength together.
Seoul Economic Daily reported that the Semiconductor R&D Center's recruitment covers multi-stage hybrid copper bonding, TSV (Through-Silicon Via) modules, and planarization of HBM copper pads. Hybrid copper bonding makes it easier to tighten bonding intervals compared to thermocompression bonding via solder bumps, leaving room to suppress package thickness at higher stack counts. On the other hand, bonding copper to copper at fine pitches requires flattening surfaces with high precision and suppressing misalignment and interface defects. There is a large gap between what can be bonded in R&D and what can be reproduced at the same quality on the factory floor.
This is where simultaneous recruitment for package development and reliability evaluation comes into play. Narrowing the bonding pitch and increasing the number of stacked layers also changes the mechanical stress on thinned dies and the degradation from thermal cycling. HBM4E's roadmap plans for 8-layer 32GB, 12-layer 48GB, and 16-layer 64GB configurations. Before moving on to HBM5, the test will be whether increases in speed and capacity can be translated into a thermal design that is actually mass-producible.
Turning Customer Qualification from an End-Point of Development into a Feedback Path
The recruitment for application engineering shows where Samsung places the completion point of a product. Even after HBM passes standalone memory tests, it won't be adopted unless it runs stably in the System in Package combined with the GPU or AI accelerator. High-speed signal jitter, power fluctuations, and heat generation all vary depending on the customer's package and cooling design. Sample shipment marks the start of customer qualification, not the completion of mass-production adoption.
Application engineers isolate issues that occur in the customer's environment and determine whether the fix belongs to the core die, base die, or package. If the fix belongs to design, circuits or timing are corrected; if it belongs to process, bonding conditions or inspection methods are reviewed. If customer qualification is treated as a separate gate that comes after development, this back-and-forth grows longer. The aim of expanding headcount in design, reliability, and packaging at the same time as application engineering is to shorten the loop that feeds evaluation results back into the next prototype.
With Custom HBM, this role becomes even more critical. Samsung plans to sequentially supply samples tailored to customers' AI accelerators and GPUs—adjusted for capacity, speed, power characteristics, and interface—starting in 2027. As customer-specific specifications multiply, the linear approach of completing a common product before handing it off for qualification becomes harder to sustain. It becomes necessary to overlap customer system design and memory development from an early stage.
Mass Production and Qualification Timelines Will Measure the Recruitment's Success
One yardstick for measuring the success of this recruitment drive is whether the gap with SK hynix, which has led the HBM market, narrows. As of March 2026, TrendForce projected that Samsung's share of global HBM bit supply would rise from 20% in 2025 to 28% in 2026, while SK hynix's share would fall from 59% to 50%. Whether that gap narrows as projected will be determined not by HBM4 performance announcements but by mass-production volumes and the pace of customer qualification.
Nor is it simply a matter of redirecting production capacity toward HBM. TrendForce estimates that the share of DRAM wafer starts allocated to HBM among the top three manufacturers will rise from 18% at the end of 2025 to 22% in 2026 and 30% in 2027. Meanwhile, in Q1 2026, DDR5 64GB RDIMM reportedly surpassed HBM in both per-wafer revenue and profitability. In a period when standard DRAM profitability is high, ramping up HBM production requires justification aligned across customer supply contracts, yield rates, and back-end process capacity.
The composition of job categories in this recruitment suggests an aim different from betting on a single bottleneck. It looks like a formation designed to advance die-to-die co-optimization, bonding and thermal design, and reliability evaluation through customer qualification all in parallel, handling the overlap between product generations. The results won't first appear at the distant point of HBM5 mass production. They'll show up in the latter half of 2026—in how fast HBM4E moves from samples to customer qualification, and whether increased HBM4 base die supply translates into shipments of finished products.