Samsung will use TSMC's 3nm process for the base die, the foundation of the stacked memory, in NVIDIA's custom high-bandwidth memory "NVHBM," Korea's Seoul Economic Daily reported on October 18, 2026. Samsung has long presented its ability to manufacture both DRAM and logic semiconductors in-house as a strength of its HBM business. According to the report, however, Samsung will outsource base die production to TSMC, prioritizing the common manufacturing conditions NVIDIA is asking of multiple memory makers. The report concerns only NVHBM for NVIDIA, and does not mean Samsung is abandoning in-house production for standard HBM. The move suggests that in HBM procurement, it is becoming important not just who supplies the memory, but also who designs the internal control circuitry and which manufacturing process produces it.
How does NVHBM change Samsung's integrated production model?
According to an exclusive report by Seoul Economic Daily, NVIDIA asked Samsung, SK hynix, and Micron to manufacture NVHBM base dies on TSMC's 3nm process. It also reportedly asked them to standardize the DRAM dies that store the data on the "1c" generation, the sixth generation of 10nm-class DRAM. Samsung's DS Division reportedly reviewed the request internally and accepted these conditions. The aim is said to be reducing differences in manufacturing methods among memory makers, limiting performance variation, and easing the validation work required for each product. These claims, however, rest on anonymous industry sources; NVIDIA and the memory makers have not officially announced the manufacturing conditions or contract details.
Samsung's conventional HBM manufacturing approach, by contrast, can be confirmed from its official announcements. In its February 2026 announcement of HBM4 mass production and shipments, Samsung explained that it used its own 1c process for the DRAM dies and its own 4nm process for the base die's logic circuitry. By tightly coordinating design and manufacturing technology between its memory and foundry divisions, and combining this with in-house advanced packaging, it said it aims to shorten production processes and lead times. At FMS in August, the company also promoted its integrated supply structure, which covers everything from design to mass production within the Samsung group.
This kind of integrated production makes it easier to reflect DRAM design changes and performance improvements in the base die's logic circuitry and even in the packaging process. But when a customer wants to source HBM with common specifications from multiple manufacturers, conforming to shared designs and manufacturing conditions may take priority over each company using its own manufacturing technology. The report says that, for NVHBM, Samsung put meeting NVIDIA's required specifications ahead of its traditional integrated production model.
That said, Samsung is not switching to external base die manufacturing across its entire HBM business. Seoul Economic Daily also reports that Samsung plans to keep its integrated production model for standard HBM and for custom HBM for other customers such as AMD. This decision should be read as a response specific to NVIDIA's NVHBM.
NVHBM's design moves GPU-side control circuitry into the HBM
A key feature of NVHBM is that it moves the memory controller, traditionally placed on the compute chip such as a GPU, into the HBM stack itself. According to NVIDIA's technical explanation published on August 26, NVHBM builds the memory controller into the HBM and combines it with a proprietary physical layer interface (PHY). The goal is to reduce the area taken up by connection circuitry so that the limited space on the compute chip can be used for computation and other tasks.
HBM has a structure in which multiple DRAM dies that store data are stacked vertically, with a base die underneath. The base die is the logic chip that connects the stacked DRAM to the adjacent GPU or dedicated AI accelerator. In NVHBM, this base die takes on memory control functions, and the method of connecting to the compute chip also changes. Rather than simply shrinking DRAM memory cells, the design aims to improve performance and power efficiency by rethinking the placement of control circuitry and the connection structure.
The "TSMC 3nm" in the report therefore refers to the process used for the logic circuitry on the base die, not to DRAM memory cells being made at 3nm. DRAM's "1c" and logic's "3nm" are manufacturing technologies for different kinds of semiconductors, so their generations and performance cannot be compared by the numbers alone. Even if each company adopts DRAM equivalent to the 1c generation, their manufacturing technologies will not necessarily be identical.
Using an outside manufacturer's advanced logic process for the HBM base die is not new. In April 2024, SK hynix announced plans to use TSMC's advanced logic process for the HBM4 base die. The goal is to integrate more functions in limited area and meet customers' differing demands for performance and power efficiency. NVIDIA's reported request can be seen as an effort to unify this division of labor between memory and logic manufacturing around NVHBM's common design.
NVIDIA says NVHBM can raise per-stack memory bandwidth by up to 30% and cut HBM power consumption by up to 15% compared with standard HBM4E. It also says the area taken up by the PHY and related support circuitry can be cut by up to 67%. These, however, are stated figures for memory bandwidth, HBM power consumption, and connection circuit area respectively. They do not mean that total GPU power consumption falls by 15% or that AI processing speed rises uniformly by 30%.
In AI inference, reading model weights and the KV cache, which holds information during generation, can limit performance. In such cases, greater memory bandwidth may shorten the time compute units spend waiting for data. However, the figures NVIDIA published describe NVHBM's design advantages, not measured results for the Samsung-made NVHBM in this report. Nor do they establish the bandwidth, power efficiency, or mass-production performance that actual products will achieve.
More memory suppliers, but manufacturing may concentrate at TSMC
NVIDIA explains that by working with major memory makers on base die design and validation for NVHBM, it will reduce the design and qualification burden for companies developing their own AI chips that incorporate NVHBM. If the Seoul Economic Daily report is accurate, this standardization extends to the base die manufacturing process as well. NVIDIA would be sourcing from several memory makers, Samsung, SK hynix, and Micron, while aiming for a configuration that uses a common base die design and TSMC's 3nm process.
The key point is that securing multiple HBM suppliers and diversifying where base dies are manufactured are separate issues. Organizing the official announcements and this report by how DRAM and base die manufacturing are divided gives the following picture.
| Product / announcement date | DRAM | Base die | What is confirmed |
|---|---|---|---|
| Samsung HBM4 (Feb. 2026) | Samsung 1c process | Samsung 4nm logic | Samsung officially announced mass production and shipments, and coordination between its divisions |
| SK hynix HBM4 (Apr. 2024) | SK hynix DRAM | Plan to use TSMC's advanced logic process | SK hynix officially announced its collaboration plan with TSMC |
| NVIDIA NVHBM (Aug. 2026) | Developed and validated with major memory makers | NVIDIA custom design | NVIDIA described reduced design and qualification burden; manufacturing process not specified |
| NVHBM at Samsung and others (Oct. 2026 report) | Reportedly requested 1c-generation standardization from all three | Reportedly requested standardization on TSMC's 3nm process | Based on industry sources cited by Seoul Economic Daily; supply volumes and mass-production timing not disclosed |
This table compares the division of manufacturing processes based on official announcements from Samsung, SK hynix, and NVIDIA, along with the Seoul Economic Daily report. Because the product generations and announcement dates differ, it does not indicate superiority in performance or production capacity.
If the reported configuration materializes, NVIDIA could secure multiple memory makers as suppliers while standardizing the base die's design and manufacturing conditions. This could reduce differences between manufacturers and lighten the burden of product validation and integration. On the other hand, if every company depends on the same TSMC 3nm process, base die manufacturing capacity could become a constraint on overall supply. Splitting the sourcing of finished HBM among several suppliers does not necessarily spread out the manufacturing of the components inside.
Standardizing manufacturing conditions also does not mean each company's NVHBM can immediately be swapped for another's. Even with the same manufacturing process and common design, qualification testing and operational validation are still needed for each product. A product must meet the capacity, bandwidth, and power consumption requirements of NVIDIA and its customers and integrate without problems into actual AI accelerators. How much procurement flexibility standardization brings can only be judged by checking final product specifications, qualification status, and each company's supply capacity.
Samsung is still evaluating in-house manufacturing
Seoul Economic Daily also reports that Samsung continues to evaluate whether it can manufacture the NVHBM base die at its own foundry. Industry sources cited by the paper say this is to prepare for the case where NVHBM demand exceeds TSMC's production capacity. In other words, adopting TSMC-made base dies to meet NVIDIA's requirements and exploring in-house manufacturing for future supply expansion are not necessarily contradictory.
However, the information that Samsung is evaluating in-house manufacturing does not mean its manufacturing process has already been qualified by NVIDIA, or that it can move to mass production right away. Changing where the base die is manufactured may require fresh validation of the combination of design and manufacturing process. Having its own foundry does not guarantee that Samsung could immediately make up any shortfall if TSMC's capacity ran short.
The decision also touches on the interests of Samsung's memory and foundry businesses. Accommodating NVIDIA's requirements even with an externally manufactured base die may let the memory business secure and expand orders from a key customer. On the other hand, if Samsung does not make the base die itself, that manufacturing business goes to TSMC. Judging the overall gains and losses for Samsung requires considering not only HBM order volumes but also manufacturing costs, profit margins, and supply terms.
Still, the report does not erase the value of Samsung's integrated production model itself. Samsung can choose to use an external foundry for products where customers demand a common design, while leveraging coordination between its memory and foundry divisions for products where distinctive performance and specifications matter. Deciding which products to produce in an integrated manner and which to build with outside partners is likely to become even more important going forward.
The key questions ahead are whether the manufacturing conditions NVIDIA is said to be demanding are officially confirmed, and whether each company's NVHBM, including Samsung's, actually gains qualification and moves to mass production. In particular, if base die manufacturing is unified on TSMC's 3nm process, it matters whether that production capacity will limit overall NVHBM supply. Can adding memory suppliers increase procurement flexibility while also securing a stable supply of common components? The answer is likely to shape mass-production plans for both NVIDIA and Samsung.