Samsung appears to be broadening its AI-oriented NAND flash lineup by use case. On October 12, 2026, ZDNet Korea reported that, in addition to the already unveiled zNAND-O, Samsung is in early development of zNAND-T, which emphasizes bandwidth, and zNAND-I, which targets performance on frequent reads and writes of small data. The latter two have not been formally announced, and there is no word on when they might become products. Still, the kind of "speed" NAND needs to deliver differs between AI running on devices and large-scale inference systems. The report suggests that the race to add storage capacity is now being joined by a race to design NAND around how data is actually used.
zNAND-O gains a bandwidth-focused T and an IOPS-focused I
zNAND-O, which Samsung unveiled at FMS 2026 in August, is a concept for edge AI. In its official announcement on August 5, Samsung said it is developing 4-layer and 8-layer versions based on V-NAND, aiming for a smaller footprint, better input/output performance and lower latency. This is not an announcement of a finished product going on sale; it is a proposal for a memory structure suited to AI.
The 4 and 8 layers here refer to the number of stacked dies, the individual semiconductor chips. Samsung's technical explanation states that 3D packaging is applied to four or eight dies. The "400+ layers" cited for V10 BV-NAND, shown at the same event, refers to stacked memory cells, which is a different structure being counted. Adding cells vertically and stacking finished dies and connecting them are separate design techniques.
According to ZDNet Korea, zNAND-T is intended for large-capacity, high-performance AI data centers and is designed to widen bandwidth, meaning the amount of data that can be moved per unit of time. It is said to stack NAND vertically and connect the dies with through-silicon vias (TSVs) that run through them. In the industry, this is positioned as HBF, or high-bandwidth flash.
zNAND-I, by contrast, targets IOPS, the number of input/output operations that can be completed per second. The outlet cites AI inference that frequently handles small amounts of temporary data, such as KV cache, as the use case. However, no specific capacity or performance figures have been given for either T or I, so the names alone do not reveal how large the performance gap is.
For KV cache, both transfer volume and access count matter
Bandwidth expresses the volume of data, while IOPS expresses the number of operations. Where performance is limited changes depending on whether large chunks of data are moved sequentially or small pieces of data are accessed over and over. Comparing IOPS figures without matching the size of the data transferred does not tell you which device can move more data. Conversely, high transfer speed does not guarantee a quick response to many small requests.
In AI inference, this difference bears on how KV cache is handled. KV cache is the intermediate attention data that a large language model reuses while generating text. Keeping earlier computation results reduces the burden of redoing the same work. On the other hand, as the input context grows longer, the data to be retained grows too, putting pressure on GPU memory.
In its September 2025 explanation of Dynamo, NVIDIA described a mechanism for moving KV cache from GPU memory to CPU memory, SSDs and storage across a network. Rather than keeping all the data from a long conversation in the GPU, the idea is to move it out as needed and reuse it. If NAND takes on the role of that destination, what matters is not only how much it can store but also how quickly the needed data can be retrieved.
Moving data does not always make things faster, however. NVIDIA states that offloading is effective when the KV cache exceeds GPU memory and the benefit of reuse outweighs the cost of transferring the data. If reading the cache back takes a long time, it can cancel out the gain from skipping computation. From this condition, designs that widen bandwidth and designs that raise I/O operation counts can be read as responses to different burdens arising in inference. Dynamo's explanation shows an approach to data placement; it does not demonstrate compatibility with zNAND-T or zNAND-I, or any speedup from them.
Same three-way split as SK hynix, but not a one-to-one match
On October 27, 2025, SK hynix officially described its "AIN Family" of AI-oriented NAND. It consists of AIN P, which emphasizes performance; AIN B, which widens bandwidth; and AIN D, which aims for higher density. Designing NAND for AI by use case predates Samsung's latest report.
Samsung's three categories are device-oriented, bandwidth and IOPS, while SK hynix's are performance, bandwidth and capacity. Even though both have "three types," the axes of classification do not line up.
| Family | Focus according to the source | Disclosure date and status |
|---|---|---|
| Samsung zNAND-O | On-device AI, smaller footprint, low latency | Official announcement on August 5, 2026. Concept unveiled; in development |
| Samsung zNAND-T | Bandwidth for AI data centers | ZDNet Korea report on October 12, 2026. Unannounced; early development |
| Samsung zNAND-I | High IOPS for inference | Same-day report by the same outlet. Unannounced; early development |
| SK hynix AIN P | I/O processing performance for inference | Official strategy presentation on October 27, 2025 |
| SK hynix AIN B | Wider bandwidth through vertical NAND stacking | Same-day official strategy presentation |
| SK hynix AIN D | High-density, large-capacity storage | Same-day official strategy presentation |
The table extracts the optimization targets and disclosure status from Samsung's announcement, ZDNet Korea's development report and SK hynix's strategy presentation. It compares the uses confirmed as of October 14, 2026, and is not a performance comparison with generations and measurement conditions aligned.
zNAND-T and AIN B, both bandwidth-focused, look close in purpose. zNAND-I and AIN P, both focused on I/O processing, could also be compared, but the names alone do not mean equivalent performance or compatibility. And zNAND-O's device-oriented category does not correspond to AIN D's emphasis on capacity. To understand the problems the two companies are trying to solve, it is better to look not at the number of families but at where each is placed and what it is designed to read and write.
The next yardstick: time to get data back to the GPU
In its FMS technical explanation, Samsung itself points to the importance of placing data according to the characteristics of memory and storage. Designs that bring data closer to the processor, designs that aim for a small footprint and low latency, and designs that handle large-capacity storage each do different jobs within a system. Adding new NAND families does not automatically settle how they will be used together.
If T and I are formally announced, the first thing to check will be the size of data and the conditions under which the performance was measured. In evaluating inference, the computation saved by reusing cache must be weighed together with the time to return data to the GPU. For devices, power consumption and mounting area are also directly tied to the use case. Lining up peak figures from different conditions will not reveal whether AI responses actually become faster.
The report offers no basis for judging shipment schedules or prices for T and I. Even so, the direction for evaluating use-specific NAND development is concrete. If the burden of returning needed data to where it is needed can be kept low, and the benefit of reusing cache outweighs it, there will be more options for handling longer contexts with limited GPU memory.