On July 8, 2026, SEALSQ and GlobalFoundries (GF) signed a strategic memorandum of understanding (MoU) to jointly develop post-quantum cryptography (PQC) security IP and cryogenic CMOS for quantum computers. With MIPS also involved, the partnership aims to create cryptographic circuits that can be embedded into SoCs and chiplets. GF's quantum business, launched in May, will also gain semiconductors for controlling and reading out qubits at cryogenic temperatures.
The timing of the announcement is not coincidental. Under a US presidential executive order issued June 22, high-value assets and high-impact systems—excluding national security systems—must migrate to PQC for key establishment by the end of 2030 and for digital signatures by the end of 2031. The phase of selecting the primary cryptographic algorithms is winding down, and a new phase has begun: competing to procure verified implementations. However, the current agreement is merely a development framework; manufacturing processes and mass-production schedules have not been decided.
From Cryptographic Algorithms to Reusable Chip Components
What the two companies plan to build first are hard macros of pre-certified PQC security IP and Chiplet Hardware Security Module (CHSM) components. A hard macro is a reusable design component whose circuit layout has already been fixed for a specific semiconductor process. Compared to redesigning cryptographic circuits for each product, this approach makes it easier to embed into SoCs while making area and timing more predictable.
CHSM is a concept that separates the circuits responsible for key generation, storage, signing, and key establishment into an independent chiplet. Combining the processor IP held by GF's subsidiary MIPS with SEALSQ's security design would enable a common component to be supplied for HSMs and secure enclaves. If realized, this would make it easier to deploy the same PQC functionality across servers, industrial equipment, and automotive systems.
That said, "pre-certified" does not mean the products are already certified. Even if ML-KEM and ML-DSA are implemented in accordance with NIST's FIPS 203 and 204, this does not mean the entire cryptographic module has passed FIPS 140-3 validation. Under NIST's Cryptographic Module Validation Program (CMVP), independent accredited testing laboratories test the modules, and NIST along with Canadian authorities review the submissions. Validation still remains on the final product side, including the configuration into which it is embedded and its operating modes.
The 2030 Procurement Deadline Is Accelerating Hardware Implementation
The main PQC schemes have already become standards. In August 2024, NIST approved ML-KEM for key establishment as FIPS 203, ML-DSA for signatures as FIPS 204, and the hash-based signature SLH-DSA as FIPS 205. The next challenge is the work of identifying where existing systems use RSA or elliptic curve cryptography and replacing them in line with update cycles.
US Executive Order 14412 attaches deadlines to this work. Excluding national security systems, federal high-value assets and high-impact systems must migrate to PQC for key establishment by December 31, 2030, and for digital signatures by December 31, 2031. NIST is to complete migration pilots by the end of 2027, and the Department of Commerce is to accelerate CMVP validation procedures within 180 days. Revisions to the Federal Acquisition Regulation are also planned, which would require FIPS-compliant PQC support from covered contractors by the end of 2030.
This demand is not confined to the United States alone. France's national cybersecurity agency, ANSSI, expects the migration to take more than a decade and recommends a hybrid approach combining classical cryptography with PQC. The agency has also stated that it would not be reasonable to newly purchase products without PQC built in after 2030. For industrial equipment and automobiles with long service lifespans, missing the next design update cycle could mean being stuck with outdated cryptography well into the 2030s.
This time lag is precisely why semiconductor IP needs to be prepared earlier than software updates. Because chips require repeated prototyping and evaluation after design, followed by certification before mass production, the process takes years. Even if hard macro development begins in 2026, the product must pass through numerous gates before it actually ships in a real product.
SEALSQ's Current Position, as Seen Through QS7001
SEALSQ already has an actual PQC semiconductor. The Quantum Shield QS7001 is equipped with an 80MHz 32-bit RISC-V CPU and a cryptographic accelerator, supporting Kyber 512/768/1024 and Dilithium 2. It carries 512K bytes of flash, 80K bytes of RAM, and 128K bytes of ROM, and operates across a temperature range of minus 40°C to 105°C. It is a secure MCU designed to serve as a hardware root of trust for industrial IoT and smart meters.
However, the product page explicitly states that Common Criteria EAL5+ evaluation is in progress and that certification has not yet been granted. According to SEALSQ's 2025 annual report, the product achieved commercial launch in Q4 2025 and development kits were shipped to customers. At the same time, no revenue has been generated as of now. Revenue is expected to begin in Q4 2026. There remains a gap between putting an algorithm onto silicon and having it adopted into a customer's mass-produced product.
Manufacturing relationships also need to be read separately. The same annual report names UMC as the manufacturing partner for QS7001. While the July 8 announcement states that new IP and CHSM will be jointly developed with GF, it does not say that QS7001 will be transferred to GF. This should not be understood as replacing the supply chain for an existing product, but rather as an agreement to create next-generation design components that can be deployed across GF's processes and customer base.
CryoCMOS Runs on a Different Timeline
This partnership also includes development for a purpose different from PQC. CryoCMOS is not a cryptographic circuit resistant to quantum attacks, but rather classical circuitry that controls qubits and reads out signals in cryogenic environments. As the number of qubits increases, so does the wiring extending from the room-temperature side, and heat inflow into the refrigerator along with signal delays makes system scaling more difficult. Bringing control circuitry closer to the quantum processor is one solution to this problem.
On May 21, GF announced the launch of Quantum Technology Solutions, stating that it would manufacture CryoCMOS for sensing, control, and readout on its FDX platform. Diraq and Equal1 are already using FDX for research into cryogenic CMOS and silicon spin qubits. GF positions itself to manufacture across superconducting, ion trap, photonic, topological, and spin qubit approaches, spanning from quantum processors to advanced packaging.
The US government is also funding this business. The US Department of Commerce and GF signed a letter of intent to provide $375 million for the expansion of Quantum Technology Solutions, and in a separate agreement, decided on a strategic investment under which the government would hold roughly 1% of GF. The CryoCMOS development with SEALSQ serves as an entry point for bringing customer-facing ASIC design into the domestic US quantum manufacturing network that GF is already building.
That said, the joint announcement only states "cryogenic" and does not specify operating temperatures, power consumption, or the target qubit modality. Nor does it state that the PQC hard macro and CryoCMOS will be placed on the same chip. While the two development efforts are connected by the word "quantum," their products, markets, and timelines for practical implementation should be tracked separately.
Three Checkpoints for Determining Progress Toward Mass Production
The first checkpoint is which of GF's processes the hard macro will be offered for. What is needed first is the timing of its inclusion in the PDK and the licensing terms. Once figures for area, power consumption, and ML-KEM/ML-DSA processing performance are released, that will indicate the stage at which customers can incorporate it into their designs.
The second is certification. Rather than the phrase "supports PQC algorithms," what should be confirmed are FIPS 140-3 or Common Criteria certificate numbers and the specific configurations covered. Even if pre-evaluated IP shortens design time, it does not automatically mean that the product into which it is embedded is certified.
The last is tape-out and customer names. Whether progress has moved from the MoU to prototype chips, customer evaluation, and mass-production contracts can be discerned from announcements accompanied by schedules and manufacturing sites. The US government's deadline has created demand. For SEALSQ and GF to capture that demand, they will need to turn reusable IP into verified silicon in time for product update cycles that occur before 2030.