- What happened: On October 22, SEEQC announced a simulated evaluation of quantum error correction that combines on-chip processing with NVIDIA Ising.
- Why it matters: The design explores finishing some processing close to the qubits, reducing the communication and decoding burden placed on GPUs.
- What to watch next: The evaluation conditions and absolute figures have yet to be disclosed, and validation on real hardware, including communication, is still outstanding.
On October 22, US-based SEEQC announced a setup in which the processing that handles quantum computer error correction is split between its own chip technology and NVIDIA's AI model, "Ising Decoding." In a system simulating a quantum processor, the company reported improvements in both the time needed to identify errors and the probability that protected quantum information becomes erroneous, compared with a configuration that uses Ising alone for preprocessing. The aim is to get some of the work done before data is handed to the GPU, easing the computation and communication load. However, this is not an announcement that the same effect was confirmed on real hardware, and some details of the evaluation conditions remain unpublished.
Handling errors before data reaches the GPU
SEEQC combined a preprocessing decoder implemented on a chip with Ising Decoding. It also positioned its own "Digital Link" and NVIDIA's "NVQLink" as frameworks connecting the quantum side and the GPU side with low latency. The design performs dedicated processing near the qubits and reduces the information passed to higher-level computers, an approach with a different focus from simply speeding up the GPU alone.
In quantum error correction, information is spread across multiple physical qubits, and clues that an error has occurred are measured repeatedly. Those measurement results are called the "syndrome." The classical computation that estimates the most likely error from the syndrome and decides what correction is needed is called decoding. Measuring to detect errors and deciding on corrections from those measurements are separate roles.
Even if syndrome results can be generated quickly, unprocessed information piles up if the decision-making cannot keep pace. What SEEQC emphasizes is that qubit errors can accumulate during this waiting time. If decisions that can be made locally are processed first, the burden on the computer examining the remainder could be lightened.
Ising, too, is a model that handles preprocessing rather than a decoder that makes the final decision on every error. A technical explanation of NVIDIA's CUDA-Q QEC 0.6 describes a configuration in which, after AI handles local errors, the syndromes it could not resolve are sent to "PyMatching" on a CPU. PyMatching is a global decoder that derives corrections from combinations of detected clues.
In other words, the idea of combining local processing with a judgment that surveys the whole already exists on the Ising side. What is new here is that SEEQC's chip technology and communication design were combined with that preprocessing configuration and compared in a simulated system. However, SEEQC's announcement does not detail the final-stage decoder or the processing order used in the integrated evaluation. NVIDIA's standard configuration diagram cannot simply be read as the implementation diagram for this work.
Disclosed and undisclosed conditions
The comparison baseline was a configuration running NVIDIA Ising as a standalone preprocessing decoder. SEEQC says it evaluated its multistage configuration in a simulated system that factored in realistic decoding latency at larger scale. It has not published how many microseconds the execution time went from and to, or what values the logical error rate changed between. The code type, its size, and the number of trials are also not stated, so there is not enough information to independently calculate the size of the improvement or its statistical variation.
One thing to keep distinct when reading the conditions is the official October 7 blog post by the company's Jerome Javelle. It deals with a "reflex decoder" that repeats local corrections while waiting for the global decoding result, and it gives specific conditions for a simulated memory experiment. That is an experiment about retaining information, and it is not described as the same test as the Ising integration evaluation here.
A table separating the disclosed conditions of the integrated evaluation from those of the separate SEEQC blog post.
| Item | October 22 Ising integration announcement | October 7 reflex decoder blog |
|---|---|---|
| Subject | Simulation of a quantum processor and system configuration | Quantum memory simulation using STIM |
| Error-correcting code | No details given | Rotated surface code with code distance 17 |
| Noise conditions | No details given | T1 = 50 μs, T2 = 30 μs. Additional gate error 10⁻⁴, readout error 2% |
| Assumed timing | Described as accounting for realistic decoding latency | Total wait time 10 μs, reflex cycle 250 ns |
| Number of trials | Not stated | Not stated |
The table compares the disclosed items in SEEQC's October 22 announcement and its official October 7 blog post. T1 and T2 are times related to energy relaxation and phase disturbance, respectively, and the values in the table are conditions fed into the simulation. The specific figures in the right column cannot be used to fill in the undisclosed parts of the left column.
The blog's reflex circuit judges check results obtained from surrounding ancilla qubits using a simple logical AND. If the conditions are met, it either issues a correction pulse or records the correction. It is described as running independently, without synchronizing or communicating with the global decoder. This approach offers a clue to why placing processing near the qubits makes sense, but it cannot be confirmed that it used the same circuit or evaluation procedure as the multistage configuration in this announcement.
Next: validating integration on real hardware, including communication
The October 22 result is, for now, a report in a corporate press release. The announcement offers no peer-reviewed paper or DOI corresponding to this integrated evaluation, and no independent replication has been found. The quantum control technology published in Nature Electronics that it mentions is a separate achievement, and its peer review must not be mistaken for verification of the decoding performance here.
Behind the Ising side is "Fast and accurate AI-based pre-decoders for surface codes" by five NVIDIA authors, including Christopher Chamberland. Published on April 14 as arXiv:2604.12841, with DOI 10.48550/arXiv.2604.12841, the version we could confirm is a preprint, and the arXiv page lists no peer-reviewed journal. The work studies passing the remaining syndromes from local AI processing to a global decoder, but it is not a paper validating this integrated configuration with SEEQC.
This report is also a comparison of simulations with different system configurations, not a study examining correlations in observational data. However, no information is given to separate how much each of the chip processing, the AI model, and the communication path contributed to the improvement. The mechanism the company describes gives reason to expect improvement, but it is not yet at the stage where one can conclude the same causal effect will be obtained on real hardware.
SEEQC's Chief Product Officer Matt Hutchings said in the announcement, "Quantum error correction is fundamentally a full-system challenge." The remark was made in the context of considering data movement and logical error rate together with decoding speed. As a next step, the company says it plans to integrate the system components shown so far and connect quantum processors and high-performance computing infrastructure chip to chip.
When the work moves to real hardware, it will need to measure the round-trip time for correction, including communication, together with the logical error rate under the same noise conditions. If the absolute values before and after the comparison and the number of trials are published and other researchers can reproduce them, there will be more material for design decisions on which tasks to hand to local dedicated chips to support quantum computation.